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rev 1.0 12/09 copyright ? 2009 by silicon laboratories si4330 si4330-b1 si4330 ism r eceiver features applications description silicon laboratories? si4330 is a highly integrated, single chip wireless ism receiver. the high-performance ezradiopro ? family includes a complete line of transmitters, receivers, and transceiv ers allowing the rf system designer to choose the optimal wireless part for their application. the si4330 offers advanced radio f eatures including c ontinuous frequency coverage from 240?960 mhz. the si4330?s high level of integration offers reduced bom cost while simp lifying the overall system design. the extremely low receive sensitivity (?121 dbm) ensure s extended range and improved link performance. built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. additional system features such as an automatic wake-up timer, low battery detector, 64 byte rx fifo, automatic pa cket handling, and preamble detection reduce overall current c onsumption and allow the us e of a lower-cost system mcu. an integrated temp erature sensor, general purpose adc, power-on-reset (por), and gpios further reduce overall system cost and size. the si4330?s digital receive architecture features a high-performance adc and dsp based modem which performs demodula tion, filtering, and packet handling for increased flexibility and performance. an easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market. ? frequency range = 240?960 mhz ? sensitivity = ?121 dbm ? low power consumption ?? 18.5 ma receive ? data rate = 0.123 to 256 kbps ? fsk, gfsk, and ook modulation ? power supply = 1.8 to 3.6 v ? ultra low power shutdown mode ? digital rssi ? wake-up timer ? auto-frequency calibration (afc) ? clear channel assessment ? programmable rx bw 2.6?620 khz ? programmable packet handler ? programmable gpios ? embedded antenna diversity algorithm ? configurable packet handler ? preamble detector ? rx 64 byte fifo ? low battery detector ? temperature sensor and 8-bit adc ? ?40 to +85 c temperature range ? integrated voltage regulators ? frequency hopping capability ? on-chip crystal tuning ? 20-pin qfn package ? low bom ? power-on-reset (por) ? remote control ? home security & alarm ? te l e m e t r y ? personal data logging ? toy control ? tire pressure monitoring ? wireless pc peripherals ? remote meter reading ? remote keyless entry ? home automation ? industrial control ? sensor networks ? health monitors ? tag readers patents pending ordering information: see page 63. pin assignments gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 xout vr_dig sclk sdi sdo vdd_dig nc vdd_rf rxn gpio_2 gpio_1 nc nc rxp nirq sdn xin nsel gpio_0 ant1 si4330
si4330-b1 2 rev 1.0 functional block diagram
si4330-b1 rev 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1. definition of test conditi ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1. serial peripheral interfac e (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2. operating mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4. system timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5. frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4. modulation options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1. fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. internal functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 5.1. rx lna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.2. rx i-q mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3. programmable gain amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.4. adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5. digital modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 5.6. synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.7. crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.8. regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 6. data handling and packet handl er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 6.1. rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 6.2. packet configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.3. packet handler rx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.4. data whitening, manchester en coding, and crc . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5. preamble detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.6. preamble length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.7. invalid pr eamble detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.8. synchronization word conf iguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.9. receive header check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7. rx modem configurati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1. modem settings for fsk and gfsk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8. auxiliary functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1. smart reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.2. microcontroller clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8.3. general purpose adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.4. temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 8.5. low battery detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
si4330-b1 4 rev 1.0 8.6. wake-up timer and 32 khz clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.7. low duty cycle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.8. gpio configurat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.9. antenna diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.10. rssi and clear channel assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9. reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 10. application notes and reference desi gns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11. customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 12. register table and descripti ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13. pin descriptions: si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 7 14. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 15. package markings (top marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.1. si4330 top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.2. top mark explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16. package outline: si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 17. pcb land pattern: si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
si4330-b1 rev 1.0 5 l ist of f igures figure 1. rx applicati on example................. .................................................................. ......... 14 figure 2. spi timing...... ............................................................ ............... ........................... ...... 16 figure 3. spi timing?read m ode .............. .................................................................. ..........17 figure 4. spi timing?burst write mode ............. ........................................................... .......... 17 figure 5. spi timing?burst read mode .. ...................................................................... .......... 17 figure 6. state machine diagram......... ........................................................................... .......... 18 figure 7. rx timing .......... ................................................................................................... ..... 22 figure 8. sensitivity at 1% per vs. carrier frequency offset .......................................... ........ 26 figure 9. pll synthesizer block diagram ................. ........................................................ ........ 30 figure 10. fifo threshold .............. ......................................................................................... .32 figure 11. packet structure............. ........................................................................... ............. .. 33 figure 12. required rx packet structure with pa cket handler disabled ....... ................ .......... 33 figure 13. multiple packets in rx pa cket handler......... ................................................. .......... 34 figure 14. multiple packets in rx with crc or header erro r ........................................... ........ 34 figure 15. operation of da ta whitening, manchester encoding , and crc ............. ................. 36 figure 16. manchester coding example ... ...................................................................... .......... 36 figure 17. header ................ ............................................................................................... ...... 38 figure 18. por glitch parameters....... ........................................................................... .......... 40 figure 19. general purpose ad c architecture .. ............................................................. .......... 42 figure 20. temperature ranges using adc8 ........... ........................................................ ........ 44 figure 21. wut interrupt and wut operat ion................. ............................................... .......... 47 figure 22. low duty cycl e mode .............. ...................................................................... .......... 48 figure 23. rssi value vs. input power. ............... ........................................................... .......... 51 figure 24. receiver?schematic receiv er?top............................................................ .......... 52 figure 25. 20-pin quad flat no-lead (qfn) ... ............................................................... ..........60 figure 26. pcb land pattern ...... .................................................................................. ............ 6 1
si4330-b1 rev 1.0 6 l ist of t ables table 1. dc characteristics 1 ................. ......................................................................... ............7 table 2. synthesizer ac el ectrical characteristics 1 ................. ............... ......................... ..........8 table 3. receiver ac el ectrical characteristics 1 ................. .......................................... ............9 table 4. auxiliary block specifications 1 ......................................................................... ..........10 table 5. digital io specifications (sdo, sdi, sclk, nsel, and nirq) ........................... ........ 11 table 6. gpio specifications (gpio_0, gpio _1, and gpio_2) ................. ................. ............ 11 table 7. absolute maximum ra tings ................. ............................................................. .......... 12 table 8. operating modes ..... .................................................................................. ............... ..15 table 9. serial interface ti ming parameters .............. .................................................. ............16 table 10. operating modes response ti me ................. ................................................. ..........18 table 11. frequency band selection ....... ...................................................................... .......... 24 table 12. packet handler registers ......... ...................................................................... .......... 35 table 13. minimum receiver settling time ................ .................................................. ............ 37 table 14. por parameters ............... .............................................. ............... .............. ............ 40 table 15. temperature sensor range ................... ........................................................ .......... 43 table 16. antenna diversity cont rol ................ ............................................................... .......... 50 table 17. register descriptions ................. .................................................................. ............ 54 table 18. package dimensions ........... ........................................................................... .......... 60 table 19. pcb land pattern dimensions ............ ........................................................... .......... 62
si4330-b1 rev 1.0 7 1. electrical specifications table 1. dc characteristics 1 parameter symbol conditions min typ max units supply voltage range v dd 1.8 3.0 3.6 v power saving modes i shutdown rc oscillator, main digital regulator, and low power digital regulator off 2 ?1550na i standby low power digital regulator on (register values retained) and main digital regulator, and rc oscillator off ? 450 800 na i sleep rc oscillator and low power digital regulator on (register values retained) and main digital regulator off ?1?a i sensor-lbd main digital regulator and low battery detector on, crystal oscillator and all other blocks off 2 ?1?a i sensor-ts main digital regulator and temperature sensor on, crystal oscillator and all other blocks off 2 ?1?a i ready crystal oscillator and main digital regulator on, all other blocks off. crysta l oscillator buffer disabled ?800? a tune mode current i tune synthesizer and regulators enabled ?8.5?ma rx mode current i rx ?18.5? ma notes: 1. all specification guaranteed by production test unless otherwise noted. prod uction test conditions and max limits are listed in the "production test conditions" section on page 13. 2. guaranteed by qualification. q ualification test conditions are listed in the "production test conditions" section on page 13.
si4330-b1 8 rev 1.0 table 2. synthesizer ac electrical characteristics 1 parameter symbol conditions min typ max units synthesizer frequency range f syn 240 ? 960 mhz synthesizer frequency resolution 2 f res-lb low band, 240?480 mhz ? 156.25 ? hz f res-hb high band, 480?960 mhz ? 312.5 ? hz reference frequency input level 2 f ref_lv when using external reference signal driving xout pin, instead of using crystal. measured peak-to-peak (v pp ) 0.7 ? 1.6 v synthesizer settling time 2 t lock measured from exiting ready mode with xosc running to any frequency. including vco calibration. ?200? s residual fm 2 ? f rms integrated over ? 250 khz bandwidth (500 hz lower bound of integration) ?2 4khz rms phase noise 2 l ? (f m ) ? f = 10 khz ? ?80 ? dbc/hz ? f = 100 khz ? ?90 ? dbc/hz ? f = 1 mhz ? ?115 ? dbc/hz ? f = 10 mhz ? ?130 ? dbc/hz notes: 1. all specification guaranteed by production test unless otherwise noted. production test conditions and max limits are listed in the "production test conditions" section on page 13. 2. guaranteed by qualification. qualificati on test conditions are listed in the "p roduction test conditions" section on page 13.
si4330-b1 rev 1.0 9 table 3. receiver ac electrical characteristics 1 parameter symbol conditions min typ max units rx frequency range f rx 240 ? 960 mhz rx sensitivity 2 p rx_2 (ber < 0.1%) (2 kbps, gfsk, bt = 0.5, ? f = ? 5khz) 3 ? ?121 ? dbm p rx_40 (ber < 0.1%) (40 kbps, gfsk, bt = 0.5, ? f = ? 20 khz) 3 ? ?108 ? dbm p rx_100 (ber < 0.1%) (100 kbps, gfsk, bt = 0.5, ? f = ? 50 khz) 3 ? ?104 ? dbm p rx_125 (ber < 0.1%) (125 kbps, gfsk, bt = 0.5, ? f = ? 62.5 khz) ? ?101 ? dbm p rx_ook (ber < 0.1%) (4.8 kbps, 350 khz bw, ook) 3 ??110 ? dbm (ber < 0.1%) (40 kbps, 400 khz bw, ook) 3 ? ?102 ? dbm rx channel bandwidth 3 bw 2.6 ? 620 khz ber variation vs power level 3 p rx_res up to +5 dbm input level ? 0 0.1 ppm lna input impedance 3 (unmatched?measured differentially across rx input pins) r in-rx 915 mhz ? 51?60j ? ? 868 mhz ? 54?63j ? 433 mhz ? 89?110j ? 315 mhz ? 107?137j ? rssi resolution res rssi ?0.5?db ? 1-ch offset selectivity 3 c/i 1-ch desired ref signal 3 db above sensitivity, ber < 0.1%. interferer and desired modu- lated with 40 kbps ? f = 20 khz gfsk with bt = 0.5, channel spacing = 150 khz ??31 ? db ? 2-ch offset selectivity 3 c/i 2-ch ??35 ? db ? ? 3-ch offset selectivity 3 c/i 3-ch ??40 ? db blocking at 1 mhz offset 3 1m block desired ref signal 3 db above sensitivity. interferer and desired modulated with 40 kbps ? f = 20 khz gfsk with bt = 0.5 ??52 ? db blocking at 4 mhz offset 3 4m block ??56 ? db blocking at 8 mhz offset 3 8m block ??63 ? db image rejection 3 im rej rejection at the image frequency. if=937 khz ??30?db spurious emissions 3 p ob_rx1 measured at rx pins ? ? ?54 dbm notes: 1. all specification guaranteed by production test unless otherwise noted. production test conditions and max limits are listed in the "production test conditions" section on page 13. 2. receive sensitivity at multiples of 30 mhz may be degraded. if channels with a multiple of 30 mhz are required it is recommended to shift the crystal frequency. contact si licon labs applications support for recommendations. 3. guaranteed by qualification. qualification test conditions are listed in t he "production test conditions" section on page 13.
si4330-b1 10 rev 1.0 table 4. auxiliary block specifications 1 parameter symbol conditions min typ max units temperature sensor accuracy 2 ts a after calibrated via sensor offset register tvoffs[7:0] ?0.5?c temperature sensor sensitivity 2 ts s ?5?mv/c low battery detector resolution 2 lbd res ?50?mv low battery detector conversion time 2 lbd ct ?250?s microcontroller clock output frequency f mc configurable to 30 mhz, 15 mhz, 10 mhz, 4 mhz, 3mhz, 2mhz, 1mhz, or 32.768 khz 32.768k ? 30m hz general purpose adc resolution 2 adc enb ?8?bit general purpose adc bit resolution 2 adc res ?4?mv/bit temp sensor & general purpose adc conversion time 2 adc ct ?305?s 30 mhz xtal start-up time t 30m using xtal and board layout in reference design. start-up time will vary with xtal type and board layout. ?600?s 30 mhz xtal cap resolution 2 30m res ?97?ff 32 khz xtal start-up time 2 t 32k ?6?sec 32 khz xtal accuracy using 32 khz xtal 2 32k res using 20 ppm 32 khz crystal ? 100 ? ppm 32 khz accuracy using internal rc oscillator 2 32krc res ?2500?ppm por reset time t por ?16?ms software reset time 2 t soft ?100?s notes: 1. all specification guaranteed by product ion test unless otherwise noted. production test conditions and max limits are listed in the "production test conditions" section on page 13. 2. guaranteed by qualification. qualification test conditions are listed in the "production test conditions" section on page 13.
si4330-b1 rev 1.0 11 table 5. digital io specifications (sdo, sdi, sclk, nsel, and nirq) parameter symbol conditions min typ max units rise time t rise 0.1 x v dd to 0.9 x v dd , c l = 5 pf ? ? 8 ns fall time t fall 0.9 x v dd to 0.1 x v dd, c l = 5 pf ? ? 8 ns input capacitance c in ??1pf logic high level input voltage v ih v dd ?0.6 ? ? v logic low level input voltage v il ?0.6 v input current i in 0=hh ??8ns fall time t fall 0.9 x v dd to 0.1 x v dd, c l = 10 pf, drv<1:0>=hh ??8ns input capacitance c in ??1pf logic high level input voltage v ih v dd ?0.6 ? v logic low level input voltage v il ??0.6v input current i in 0=ll 0.1 0.5 0.8 ma i omaxlh drv<1:0>=lh 0.9 2.3 3.5 ma i omaxhl drv<1:0>=hl 1.5 3.1 4.8 ma i omaxhh drv<1:0>=hh 1.8 3.6 5.4 ma logic high level output voltage v oh i oh < i omax source, v dd =1.8 v v dd ?0.6 ? ? v logic low level output voltage v ol i ol < i omax sink, v dd =1.8 v ??0.6v note: all specifications guaranteed by qualification. qualification test conditions ar e listed in the "production test conditions" section on page 13.
si4330-b1 12 rev 1.0 table 7. absolute maximum ratings parameter value unit v dd to gnd ?0.3, +3.6 v voltage on digital control inputs ?0.3, v dd + 0.3 v voltage on analog inputs ?0.3, v dd + 0.3 v rx input power +10 dbm operating ambient temperature range t a ?40 to +85 ? c thermal impedance ? ja 30 ? c / w junction temperature t j +125 ? c storage temperature range t stg ?55 to +125 ? c note: stresses beyond those listed under ?absolute maximum ra tings? may cause permanent damage to the device. these are stress ratings only and functional operation of the devic e at or beyond these ratings in the operational sections of the specifications is not implied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. caution: esd sensitive device.
si4330-b1 rev 1.0 13 1.1. definition of test conditions production test conditions: ? t a =+25c ? v dd =+3.3vdc ? sensitivity measured at 919 mhz ? external reference signal (xout) = 1.0 v pp at 30 mhz, centered around 0.8 vdc ? production test schematic (unless noted otherwise) ? all rf input and output levels referred to the pins of the si4330 (not the rf module) extreme test conditions: ? t a = ?40 to +85 c ? v dd = +1.8 to +3.6 vdc ? using 4330-t-b1-b-xxx reference de sign or production test schematic ? all rf input levels referred to the pins of the si4330 (not the rf module)
si4330-b1 14 rev 1.0 2. functional description the si4330 is an ism wireless receiver with contin uous frequency tuning over the specified bands which encompasses from 240?960 mhz. the wide operating voltage range of 1.8?3.6 v and low current consumption makes the si4330 an ideal solution for battery powered applications. the si4330 receiver uses a single-conversion mixe r to downconvert the 2-level fsk/gfsk/ook modulated receive signal to a low if frequency. following a programmable gain amplifier (pga) the signal is converted to the digital domain by a high performance ?? adc allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in dsp incr easing the receiver?s performance and flexibility versus analog based architectures. the demodulated signal is then output to the system mcu through a programmable gpio or via the standard spi bus by reading the 64-byte rx fifo. a high precision local osc illator (lo) is generated by an integrated vco and ?? fractional-n pll synthesizer. the synthesizer is designed to support co nfigurable data rates, output freque ncy and frequency deviation at any frequency between 240?960 mhz. the si4330 supports frequency hopping and antenna divers ity switch control to extend the link range and improve performance. antenna diversity is completely integrated into the si4330 and can improve the system link budget by 8?10 db, resulting in substantia l range increases depending on the environmental conditions. the si4330 is designed to work with a microcontroller, crysta l, and a few external components to create a very low cost system. voltage regulators are integrated on-chip which allows for a wide operat ing supply voltage range from +1.8 to +3.6 v. a standard 4-pin spi bus is used to communicate with an external microcontroller. three configurable general purpose i/os are available. a complete list of the available gpio functions is shown in "8. auxiliary functions" on page 40 and includes microcontroller clock ou tput, antenna diversi ty, antenna switch, por, and various interrupts. a complete list of the available gpio functions is shown in an467: si4330 register descriptions.? figure 1. rx application example x1 30 mhz supply voltage microcontroller vdd vss gp1 gp2 gp3 gp4 100 n c4 100 p c5 c3 1 u l1, c1, and c2 values depend on frequency band, and antenna impedance. programmable load capacitors for x1 are integrated. vdd_rf sclk 19 18 17 16 1 2 3 4 15 14 13 7 8 9 10 sdi sdo vdd_d rxn nc rfp gpio0 gpio1 vr_dig nirq sdn xout nsel gpio2 5 nc 6 ant1 nc 20 xin 11 12 gp5 c6 1 u l1 c1 c2 si4330
si4330-b1 rev 1.0 15 2.1. operating modes the si4330 provides several operating modes which can be used to optimize the power consumption for a given application. depending upon the system communication prot ocol, an optimal trade-off between the radio wake time and power consumption can be achieved. table 8 summarizes the operating modes of the si4330. in general, any given operating mode may be classified as an active mode or a power saving mode. the table indicates which block(s) are enabled (active) in each corresponding mode. with the exception of the shutdown mode, all can be dynamically selected by sending the appropriate commands over the spi operating mode. an ?x? in any cell means that, in the given mode of operation, that block can be independently programmed to be eith er on or off, without noticeably impacting the current consumption. the spi circuit block includes the spi inte rface hardware and the device register space. the 32 khz osc block includes the 32.768 khz rc oscillator or 32.768 khz crystal oscillator and wake-up timer. aux (auxiliary blocks) includes the te mperature sensor, general purpose adc, and low-battery detector. table 8. operating modes mode name circuit blocks digital ldo spi 32 khz osc aux 30 mhz xtal pll rx i vdd shutdown off (register contents lost) off off off off off off 15 na standby on (register contents retained) on off off off off off 450 na sleep on on x off off off 1 a sensor on x on off off off 1 a ready on x x on off off 800 a tuning on x x on on off 8.5 ma receive on x x on on on 18.5 ma
si4330-b1 16 rev 1.0 3. controller interface 3.1. serial periph eral interface (spi) the si4330 communicates with the host mcu over a stan dard 3-wire spi interface: sclk, sdi, and nsel. the host mcu can read data from the device on the sdo ou tput pin. a spi transaction is a 16-bit sequence which consists of a read-write (r /w) select bit, followed by a 7-bit address field (addr), and an 8-bit data field (data) as demonstrated in figure 2. the 7-bit address field is used to select one of the 128, 8-bit control registers. the r /w select bit determines whether the spi transa ction is a read or write transaction. if r /w = 1 it signifies a write transaction, while r /w = 0 signifies a read transaction. the contents (addr or data) are latched into the si4330 every eight clock cycles. the timing parameters for the spi interface are shown in table 9. the sclk rate is flexible with a maximum rate of 10 mhz. figure 2. spi timing to read back data from the si4330, the r/w bit must be se t to 0 followed by the 7-bit address of the register from which to read. the 8 bit data field following the 7-bit addr field is ignored n the sdi pin when r/w = 0. the next eight negative edge tran sitions of the sclk signal will clock out the contents of the selected register. the data read from the selected register will be availa ble on the sdo output pin. the read f unction is shown in figure 3. after the read function is completed the sdo pin will remain at either a logic 1 or logic 0 state depending on the last data bit clocked out (d0). when nsel goes high the sdo output pin will be pulled high by internal pullup. table 9. serial interface timing parameters symbol parameter min (nsec) diagram t ch clock high time 40 t cl clock low time 40 t ds data setup time 20 t dh data hold time 20 t dd output data delay time 20 t en output enable time 20 t de output disable time 50 t ss select setup time 20 t sh select hold time 50 t sw select high period 80 nsel sclk sdi msb lsb a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a4 xx xx a3 rw a7 a6 a5 rw data address sdi sclk sdo nsel t cl t ch t ds t dh t dd t ss t e n t sh t de t sw
si4330-b1 rev 1.0 17 figure 3. spi timing?read mode the spi interface contains a burst read /write mode which allows for reading/ writing sequential registers without having to re-send the spi address. when the nsel bit is held low while continuing to send sclk pulses, the spi interface will automatically increment th e addr and read from/write to the next address. an example burst write transaction is illustrate d in figure 4 and a burst read in figure 5. as long as nsel is held low, input data will be latched into the si4330 every eight sclk cycles. figure 4. spi timing?burst write mode figure 5. spi timing?burst read mode nsel sclk sdi first bit last bit a0 d7 =x sdo d7 a1a2 first bit last bit a3 d6 =x d5 =x d4 =x d3 =x d2 =x d1 =x d0 =x d6 d5 d4 d3 d2 d1 d0 a4 a5 a6 rw =0 nsel sclk sdi first bit a0 d7 =x a1 a2 a3 d6 =x d5 =x d4 =x d3 =x d2 =x d1 =x d0 =x a4 a5 a6 rw =1 last bit d7 =x d6 =x d5 =x d4 =x d3 =x d2 =x d1 =x d0 =x nsel sclk sdi first bit last bit a0 d7 =x sdo d7 a1 a2 first bit a3 d6 =x d 5 =x d 4 =x d3 =x d2 =x d1 =x d0 =x d6 d5 d4 d3 d2 d1 d0 a4 a5 a6 rw =0 d7 d6 d5 d4 d3 d2 d1 d0
si4330-b1 18 rev 1.0 3.2. operating mode control there are three primary states in the si4330 radio stat e machine: shutdown, idle, and rx (see figure 6). the shutdown state completely shuts down the radio to mi nimize current consumption. there are five different configurations/options for the idle state which can be sele cted to optimize the chip to the applications needs. "register 07h. operating mode and function control 1" co ntrols which operating mode/s tate is selected with the exception of shutdown which is controlled by sdn pin 20. the rx state may be reached automatically from any of the idle states by setting the rxon bit in "registe r 07h. operating mode and function control 1". table 10 shows each of the operating modes with the time required to reach rx mode as well as the current consumption of each mode. the si4330 includes a low-power digital regulated supply (l pldo) which is internally co nnected in parallel to the output of the main digital regulator (a nd is available externally at the vr _dig pin). this common digital supply voltage is connected to all digital ci rcuit blocks including the digital modem, crystal oscillator, spi, and register space. the lpldo has extremely low qu iescent current consumption but limited current supply capability; it is used only in the idle-standby and idle-sleep modes. th e main digital regulator is automatically enabled in all other modes. figure 6. state machine diagram table 10. operating modes response time state/mode response time to rx current in state /mode [a] shut down state 16.8 ms 15 na idle states: standby mode sleep mode sensor mode ready mode tune mode 800 s 800 s 800 s 200 s 200 s 450 na 1a 1a 800 a 8.5 ma rx state na 18.5 ma shut dwn idle* rx * five different options for idle shutdown
si4330-b1 rev 1.0 19 3.2.1. shutdown state the shutdown state is the lowest current consumption state of the device with nominally less than 15 na of current consumption. the shutdown state may be entere d by driving the sdn pin (pin 20) high. the sdn pin should be held low in all states e xcept the shutdown state. in the shutdown state, the contents of the registers are lost and there is no spi access. when the chip is connected to the power supply, a por will be initiated after the falling edge of sdn. 3.2.2. idle state there are five different modes in the idle state which may be selected by "register 07h. operating mode and function control 1". all modes have a tradeoff between cu rrent consumption and response time to rx mode. this tradeoff is shown in table 10. after the por event, swreset, or exiting from the shutdown state the chip will default to the idle-ready mode. after a por event the inte rrupt registers must be read to properly enter the sleep, sensor, or standby mode and to control the 32 khz clock correctly. 3.2.2.1. standby mode standby mode has the lowest current consumption of th e five idle states with only the lpldo enabled to maintain the register values. in this mode the regist ers can be accessed in both read and write mode. the standby mode can be entered by writ ing 0h to "register 07h. operating mode and function control 1". if an interrupt has occurred (i.e., the nirq pin = 0) the interr upt registers must be read to achieve the minimum current consumption. additionally, the adc should not be selected as an input to th e gpio in this mode as it will cause excess current consumption. 3.2.2.2. sleep mode in sleep mode the lpldo is enabled along with the wake -up-timer, which can be used to accurately wake-up the radio at specified intervals. see "8.6. wake-u p timer and 32 khz clock source" on page 46 for more information on the wake -up-timer. sleep mode is entered by setting enwt = 1 (40h) in "regi ster 07h. operating mode and function control 1". if an interrupt has occurred (i.e., the nirq pin = 0) the interrupt registers must be read to achieve the minimum current consumption. also, the adc should not be selected as an input to the gpio in this mode as it will caus e excess curren t consumption. 3.2.2.3. sensor mode in sensor mode either the low battery detector, temperature sensor, or both may be enabled in addition to the lpldo and wake-up-timer. the low battery detector can be enabled by setting enlbd = 1 in "register 07h. operating mode and function control 1". see "8.4. temperature sensor" on page 43 and "8.5. low battery detector" on page 45 for more information on these featur es. if an interrupt has occurred (i.e., the nirq pin = 0) the interrupt registers must be read to achieve the minimum current consumption. 3.2.2.4. ready mode ready mode is designed to give a fast transition time to rx mode with reasonable current consumption. in this mode the crystal oscillator remains enabled reducing the time required to switch to rx mode by eliminating the crystal start-up time. ready mode is entered by setting xton = 1 in "register 07h. operating mode and function control 1". to achieve the lowest curr ent consumption state the crystal osc illator buffer should be disabled in ?register 62h. crystal oscillator control and test.? to exit ready mode, bufo vr (bit 1) of this register must be set back to 0. 3.2.2.5. tune mode in tune mode the pll remains enabled in addition to th e other blocks enabl ed in the idle modes. this will give the fastest response to rx mode as the pll will remain locked but it results in the highest current consumption. this mode of operation is designed for frequency hopp ing spread spectrum syste ms (fhss). tune mode is entered by setting pllon = 1 in "register 07h. operating mode and function control 1". it is not necessary to set xton to 1 for this mode, the internal state mach ine automatically enables the crystal oscillator.
si4330-b1 20 rev 1.0 3.2.3. rx state the rx state may be entered from any of the idle modes wh en the rxon bit is set to 1 in "register 07h. operating mode and function control 1". a built-in sequencer takes ca re of all the actions required to transition from one of the idle modes to the rx state. the following sequence of events will occur automatically to get the chip into rx mode when going from standby mode to rx mode by setting the rxon bit: 1. enable the main digital ldo and the analog ldos. 2. start up crystal oscillator and wait unt il ready (controlled by an internal timer). 3. enable pll. 4. calibrate vco (this action is skipped when the vcocal bit is ?0?, default value is ?1?). 5. wait until pll settles to required receive frequency (controlled by an internal timer). 6. enable receive circuits: lna, mixers, and adc. 7. enable receive mode in the digital modem. depending on the configuration of the radio all or some of the following functions will be perfo rmed automatically by the digital modem: agc, afc (optional), update status registers, bit synchronization, packet handling (optional) including sync word, header check, and crc. 3.2.4. device status the operational status of the chip can be read from "register 02h. device status". add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 02 r device status ffovfl ffunfl rxffem headerr freqerr cps[1] cps[0] ?
si4330-b1 rev 1.0 21 3.3. interrupts the si4330 is capable of generating an interrupt signal when certain events occur. the chip notifies the microcontroller that an interrupt event has occurred by setting the nirq output pin low = 0. this interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the interrupt status bits) shown below occur. the nirq pin will remain low until the microcont roller reads the inte rrupt status regi ster(s) (registers 03h?04h) containing the active interrupt status bit. the nirq output si gnal will then be reset until the next change in status is detected. the interrupts must be enabled by the corresponding enable bit in the interrupt enable registers (registers 05h?06h). all enabled interrupt bits will be cleare d when the microcontroller reads the interrupt status register. if the interrupt is not enab led when the event occurs it will not trigger the nirq pin, but the status may still be read at anytime in the interrupt status registers. for a complete descriptions of each interrupt, see ?an467: si4330 register descriptions.? add r/w function/descript ion d7 d6 d5 d4 d3 d2 d1 d0 por def. 03 r interrupt status 1 ifferr reserved reser ved irxffafull iext reserved ipkvalid icrcerror ? 04 r interrupt status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor ? 05 r/w interrupt enable 1 enfferr reserved reserv ed enrxffafull enext reserved enpkvalid encrcerror 00h 06 r/w interrupt enable 2 enswdet enpreaval en preainval enrssi enwut enlbd enchiprdy enpor 01h
si4330-b1 22 rev 1.0 3.4. system timing the system timing for rx mode is shown in figure 7. the user only needs to program the desired mode, and the internal sequencer will properly transition the part from its current mode. the vco will automatically calibrate at every frequency change or power up. the pll t0 time is to allow for bias settling of the vco. the pll ts time is for the settling ti me of the pll, which has a default setting of 100 s. the total time for pll t0, pll cal, and pll ts under all co nditions is 200 s. under certain applications, the pll t0 time and the pll cal may be skipped for faster turn-arou nd time. contact applications support if faster turnaround time is desired. figure 7. rx timing rx packet xtal settling time pll t0 pll cal pllts 600us configurable 0-70us, default =50us 50us, may be skipped configurable 0-310us, recommend 100us
si4330-b1 rev 1.0 23 3.5. frequency control for calculating the necessar y frequency register settings it is re commended that custom ers use silicon labs? wireless design suite (wds) or the ezradiopro register calculator worksheet (in microsoft excel) available on the product website. these methods offe r a simple method to quickly determi ne the correct settings based on the application requirements. the following information can be used to calculated these values manually. 3.5.1. frequency programming in order to receive an rf signal, the desired channel frequency, f carrier , must be programmed into the si4330. note that this frequency is the center frequency of the desir ed channel and not an lo frequency. the carrier frequency is generated by a fractional-n synthes izer, using 10 mhz both as the reference frequency and the clock of the (3 rd order) ? modulator. this modulator uses modulo 64000 accumulators. this design was made to obtain the desired frequency resolution of the synthesizer. the overall division ratio of the feedback loop consist of an integer part (n) and a fractional part (f). in a generic sense, the output frequency of the synthesizer is as follows: the fractional part (f) is determined by three differ ent values, carrier frequency (fc[15:0]), frequency offset (fo[8:0]), and frequency deviation (fd[7:0]). due to the fi ne resolution and high loop bandwidth of the synthesizer, fsk modulation is applied inside the loop and is done by varying f according to the incoming data; this is discussed further in "3.5.4. frequency offset adjustment " on page 26. also, a fixed offset can be added to fine- tune the carrier frequency and counteract crystal toleranc e errors. for simplicity assume that only the fc[15:0] register will determine the fractional component. the equation for selectio n of the carrier frequency is shown below: the integer part (n) is determined by fb[4:0]. additional ly, the frequency can be halved by connecting a 2 divider to the output. this divider is not inside the loop and is controlled by the hbsel bit in "register 75h. frequency band select." this effectively partitions the entire 240?960 mhz frequency range into two separate bands: high band (hb) for hbsel = 1, and low band (lb) for hbsel = 0. the valid range of fb[4:0] is from 0 to 23. if a higher value is written into the register, it will default to a value of 23. the integer part has a fi xed offset of 24 added to it as shown in the formula above. table 11 demonstrates the selection of fb[4:0] for the corresponding frequency band. after selection of the fb (n) the fractional component may be solved with the following equation: fb and fc are the actual numbers stor ed in the corresponding registers. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 73 r/w frequency offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 74 r/w frequency offset 2 reserved reserved res erved reserved reserved reserved fo[9] fo[8] 00h 75 r/w frequency band select reserved sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 35h 76 r/w nominal carrier frequency 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] bbh 77 r/w nominal carrier frequency 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h )(10 fnmhz f out u )()1(10 fn hbsel mhz f carrier u u ) 64000 ]0:15[ 24]0:4[(*)1(*10 fc fb hbsel mhz f carrier 64000*24]0:4[ )1(*10 ]0:15[ ? ? 1 ? fb hbsel mhz f fc carrier
si4330-b1 24 rev 1.0 the chip will automatically shift the fr equency of the synt hesizer down by 937.5 khz (3 0 mhz 32) to achieve the correct intermediate frequency (if) when rx mode is entered. low-side injection is used in the rx mixing architecture. table 11. frequency band selection fb[4:0] value n frequency band hbsel=0 hbsel=1 0 24 240?249.9 mhz 480?499.9 mhz 1 25 250?259.9 mhz 500?519.9 mhz 2 26 260?269.9 mhz 520?539.9 mhz 3 27 270?279.9 mhz 540?559.9 mhz 4 28 280?289.9 mhz 560?579.9 mhz 5 29 290?299.9 mhz 580?599.9 mhz 6 30 300?309.9 mhz 600?619.9 mhz 7 31 310?319.9 mhz 620?639.9 mhz 8 32 320?329.9 mhz 640?659.9 mhz 9 33 330?339.9 mhz 660?679.9 mhz 10 34 340?349.9 mhz 680?699.9 mhz 11 35 350?359.9 mhz 700?719.9 mhz 12 36 360?369.9 mhz 720?739.9 mhz 13 37 370?379.9 mhz 740?759.9 mhz 14 38 380?389.9 mhz 760?779.9 mhz 15 39 390?399.9 mhz 780?799.9 mhz 16 40 400?409.9 mhz 800?819.9 mhz 17 41 410?419.9 mhz 820?839.9 mhz 18 42 420?429.9 mhz 840?859.9 mhz 19 43 430?439.9 mhz 860?879.9 mhz 20 44 440?449.9 mhz 880?899.9 mhz 21 45 450?459.9 mhz 900?919.9 mhz 22 46 460?469.9 mhz 920?939.9 mhz 23 47 470?479.9 mhz 940?960 mhz
si4330-b1 rev 1.0 25 3.5.2. easy frequency programming for fhss while registers 73h?77h may be used to program the carrier frequency of the si4330, it is often easier to think in terms of ?channels? or ?channel numbers? rather than an absolute frequency value in hz. also, there may be some timing-critical applications (such as for frequency hoppin g systems) in which it is desirable to change frequency by programming a single register. once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. a nominal frequency is first set using registers 73h?77h, as described above. registers 79h and 7ah are then used to set a channel step size and channel number, relative to the nominal setting. the frequency hopping step size (fhs [7:0]) is set in incremen ts of 10 khz with a maximum channel step size of 2.56 mhz. the frequency hopping channel select register then selects channels based on multiples of the step size. for example, if the nominal frequency is set to 900 mhz using registers 73h?77h, the channel step size is set to 1 mhz using "register 7ah. frequency hopping step si ze," and "register 79h. frequency hopping channel select" is set to 5d, the resulting carrier frequency would be 905 mhz. once the nominal frequency and channel step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to change the frequency. 3.5.3. automatic state transition for frequency change if registers 79h or 7ah are changed in rx mode, the st ate machine will automatically transition the chip back to tune and change the frequency. this fe ature is useful to reduce the number of spi commands required in a frequency hopping system. this in turn reduces microcontroller activity, reducing current consumption. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 79 r/w frequency hopping channel select fhch[7] fhch[6] fhch[5 ] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h 7a r/w frequency hopping step size fhs[7] fhs[6] fhs[5] fhs[4] fh s[3] fhs[2] fhs[1] fhs[0] 00h )10]0:7[(]0:7[ khz fhch fhsfnom f carrier ? ? ? ?
si4330-b1 26 rev 1.0 3.5.4. frequency offset adjustment when the afc is disabled the frequency offset can be adjust ed manually by fo[9:0] in registers 73h and 74h. it is not possible to have both afc and offset as internally they share the same register. the frequency offset adjustment and the afc both are implemented by shifting the synthesize r local oscillator frequency. this register is a signed register so in order to ge t a negative offset it is necessary to take the twos complement of the positive offset number. the offset can be calculated by the following: the adjustment range in high band is 160 khz and in low band it is 80 khz. for example to compute an offset of +50 khz in high band mode fo[9:0] should be set to 0a0h. for an offset of ?50 khz in high band mode the fo[9:0] register should be set to 360h. 3.5.5. automatic frequency control (afc) all afc settings can be easily obtained from the settings calculator. this is the recommended method to program all afc settings. this section is inten ded to describe the operation of the afc in more detail to help understand the trade-offs of using afc. the receiver supports automa tic frequency control (afc) to compensate for frequency differences between the transmitter and receiver reference frequencies. these differences can be caused by the absolute accuracy and temperature dependencies of the re ference crystals. due to frequency offset compensation in the modem, the receiver is tolerant to frequency offs ets up to 0.25 times the if bandwidth when the afc is disabled. when the afc is enabled, the received signal will be center ed in the pass-band of the if filter, providing optimal sensitivity and selectivity over a wider range of frequency offsets up to 0.35 times the if bandwidth. the trade-off of receiver sensitivity (at 1% per) versus carrier offset and the im pact of afc are illustrated in figure 9. figure 8. sensitivity at 1% per vs. carrier frequency offset add r/w function/descripti on d7 d6 d5 d4 d3 d2 d1 d0 por def. 73 r/w frequency offset fo[7] fo[6] fo [5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 74 r/w frequency offset reserved reserved rese rved reserved reserved re served fo[9] fo[8] 00h ]0:9[)1(25.156 fo hbselhz set desiredoff ? ? ? ? )1(25.156 ]0:9[ ?? ? hbselhz set desiredoff fo
si4330-b1 rev 1.0 27 when afc is enabled, the preamble length needs to be long enough to settle the afc. in general, one byte of preamble is sufficient to se ttle the afc. disabling the afc allows the preamble to be shortened from 40 bits to 32 bits. note that with the afc disabled , the preamble leng th must still be long enough to settle the receiver and to detect the preamble (see "6.6. preamble length" on page 37). the afc corrects the detected frequency offset by changing the frequency of the fracti onal-n pll. when the pr eamble is detected, the afc will freeze for the remainder of the packet. in multi-packet mode, the afc is reset at the end of every packet and will re-acquire the frequency offset for the next packet. the afc loop in cludes a bandwidth limiting mechanism improving the rejection of out of band signals. when the afc loop is enabled, its pull-in-range is determined by the bandwidth limiter value (afclimiter) which is located in register 2ah. afc_pull_in_range = afclimiter[7:0] x (hbsel+1) x 625 hz the afc limiter register is an unsigned register and its value can be obtained from the ezradiopro register calculator spreadsheet. frequency correction afc disabled freq offset register afc enabled afc
si4330-b1 28 rev 1.0 4. modulation options 4.1. fifo mode in fifo mode, the receive data is stored in integrated fifo register memory. the fifos are accessed via "register 7fh. fifo access," and are most efficiently ac cessed with burst read/write operation as discussed in "3.1. serial peripheral interface (spi)" on page 16. in rx mode, only the bytes of the received packet struct ure that are considered to be "data bytes" are stored in fifo memory. which bytes of the received packet are considered "data bytes" is determined by the automatic packet handler (if enabled), in conjunction with the pack et handler registers (see table 12 on page 35). if the automatic packet handler is disabled, all bytes following the sync word are considered data bytes and are stored in fifo memory. thus, even if automatic packet handling operation is not desired, the preamble detection threshold and sync word still need to be programmed so that th e rx modem knows when to start filling data into the fifo. when the fifo is being used in rx mode, all of the received data may still be obs erved directly (in real- time) by properly programming a gpio pin as the rxdata ou tput pin; this can be quite useful during application development. when in fifo mode, the chip will automatically exit the rx state when either the ipks ent or ipkvalid interrupt occurs. the chip will return to any of the other states based on the settings in "registe r 07h. operat ing mode and function control 1." in rx mode, the rxon bit will be cleared if ipkvalid occurs and th e rxmpk bit (rx multi-packe t bit, spi register 08h bit [4]) is not set. when the rxmpk bit is set, the part will not exit the rx stat e after successfully receiving a packet, but will remain in rx mode. the micr ocontroller will need to decide on the appropriat e subsequent action, depending upon information such as an interrupt generated by crc, packet valid, or preamble detect.
si4330-b1 rev 1.0 29 5. internal functional blocks this section provides an overview some of the key blocks of the internal radio architecture. 5.1. rx lna the input frequency range for the lna is between 240? 960 mhz. the lna provides gain with a noise figure low enough to suppress the noise of the following stages. the lna has one step of gain control which is controlled by the analog gain control (agc) algorithm. the agc algorithm adjusts the gain of the lna and pga so the receiver can handle signal levels from sensitivity to +5 dbm with optimal performance. 5.2. rx i-q mixer the output of the lna is fed internally to the input of the receive mixer. the receive mixer is implemented as an i-q mixer that provides both i and q channel outputs to the programmable gain amplifier. the mixer consists of two double-balanced mixers whose rf inputs are driven in parallel, local oscillato r (lo) inputs are dr iven in quadrature, and separate i and q i ntermediate f requency (if) outputs drive the prog rammable gain amplifier. the receive lo signal is supplied by an integrated vco and pll syn thesizer operating between 240?960 mhz. the necessary quadrature lo signals are derived from the divider at the vco output. 5.3. programmable gain amplifier the programmable gain amplifier (pga) provides the necessary gain to boost the signal level into the dynamic range of the adc. the pga must also have enough gain switching to allow for large input signals to ensure a linear rssi range up to ?20 dbm. the pga has steps of 3 db which are controlled by the agc algorithm in the digital modem. 5.4. adc the amplified iq if signals are digitized using an analog -to-digital converter (adc), which allows for low current consumption and high dynamic range. the bandpass response of the adc provides exce ptional rejection of out of band blockers. 5.5. digital modem using high-performance adcs allows ch annel filtering, image rejection, and demodulation to be performed in the digital domain, resulting in reduced area while increa sing flexibility. the digital modem performs the following functions: ? channel selection filter ? rx demodulation ? agc ? preamble detector ? invalid preamble detector ? radio signal strength indicator (rssi) ? automatic frequency compensation (afc) ? packet handling including ezmac tm features ? cyclic redundancy check (crc) the digital channel filter and demodulator are optimized for ultra low power consumption and are highly configurable. supported modulation types are gfsk, f sk, and ook. the channel filter can be configured to support bandwidths ranging from 620 khz down to 2.6 khz . a large variety of data rates are supported ranging from 0.123 up to 256 kbps. the agc algorithm is implement ed digitally using an advanced control loop optimized for fast response time. the configurable preamble detector is used to improve the relia bility of the sync-word de tection. the sync-word detector is only enabled when a valid preamble is detected, significantly reducing the probabilit y of false detection. the received signal strength indicato r (rssi) provides a measure of the si gnal strength received on the tuned channel. the resolution of the rssi is 0.5 db. this high resolution rssi enables accurate channel power
si4330-b1 30 rev 1.0 measurements for clear channel assessment ( cca), and carrier sense (cs) functionality. frequency mistuning caused by crystal inaccuracies c an be compensated by enabling the digital automatic frequency control (afc) in receive mode. a comprehensive programma ble packet handler including key features of silicon labs? ezmac tm is integrated to create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. the extensive programmability of the packet header allows for advanced pa cket filtering which in turn enables a mix of broadcast, group, and point-to-point communication. a wireless communication channel can be corrupted by no ise and interference, and it is therefore important to know if the received data is free of errors. a cyclic redundancy check (crc) is us ed to detect the presence of erroneous bits in each packet. a crc is computed an d appended at the end of each transmitted packet and verified by the receiver to confirm that no errors ha ve occurred. the packet handler and crc can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller. 5.6. synthesizer an integrated sigma delta ( ? ) fractional-n pll synthesizer capable of operating from 240?960 mhz is provided on-chip. using a ? synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. the pll and ' - 6 modulator scheme is designed to support any desired frequency and channel spacing in the range from 240?960 mhz with a frequency resolution of 156.25 hz (low band) or 312.5 hz (high band). figure 9. pll synthesizer block diagram the reference frequency to the pll is 10 mhz. the pll utilizes a differential l- c vco, with integrated on-chip inductors. the output of the vco is fo llowed by a configurable divider whic h will divide down the signal to the desired output frequency band. the modu lus of the variable divide-by-n divi der stage is controlled dynamically by the output from the ' - 6 modulator. the tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 hz anywhere in the range between 240?960 mhz. 5.6.1. vco the output of the vco is automatically divided down to the correct output frequency depending on the hbsel and fb[4:0] fields in "register 75h. frequ ency band select." in receive mode, the lo frequency is automatically shifted downwards by the if frequency of 937.5 khz, allowing receive operation on the same frequency. the vco integrates the resonator inductor and tuning varact or, so no external vco components are required. the vco uses a capacitance bank to cover the wide frequency range sp ecified. the capacitance bank will automatically be calibrated every time the synthesizer is enabled. in certain fast hopping applications this might not be desirable so the vco calibration may be skipped by setting the appropriate register. n lpf cp pfd fref = 10 m vco selectable divider rx
si4330-b1 rev 1.0 31 5.7. crystal oscillator the si4330 includes an integrated 30 mhz crystal oscillator with a fast star t-up time of less than 600 s when a suitable parallel resonant crystal is used. the design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external compon ents. by default, all that is required off-chip is the 30 mhz crystal. the crystal load capacitance can be digitally programme d to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal oscillator. the tuning of t he crystal load capacitance is programmed through the xlc[6: 0] field of "register 09h. 30 mhz crysta l oscillator load capacitance." the total internal capacitance is 12.5 pf and is adj ustable in approximately 127 steps (97ff/step). the xtalshift bit provides a coarse shift in frequency but is not binary with xlc[6:0]. the crystal frequency adjustment can be used to compensate for crystal production tolerances. utilizing the on- chip temperature sensor and suitable control softwa re, the temperature depende ncy of the crystal can be canceled. the typical value of the total on-chip capa citance cint can be calculated as follows: cint = 1.8 pf + 0.085 pf x xlc[6:0] + 3.7 pf x xtalshift note that the coarse shift bit xtalshift is not binary with xlc[6:0]. the total load capacitance cload seen by the crystal can be calculated by adding the sum of all external para sitic pcb capacitances cext to cint. if the maximum value of cint (16.3 pf) is not sufficient, an external capacito r can be added for exact tuning. additional information on calculating cext and crystal selecti on guidelines is provided in ?an417: si4x3x family crystal oscillator.? if afc is disabled then the synthesizer frequency may be further adjusted by programming the frequency offset field fo[9:0]in "register 73h. frequen cy offset 1" and "register 74h. frequen cy offset 2", as discussed in "3.5. frequency control" on page 23. the crystal oscillator fr equency is divided down internally and may be output to the mi crocontroller through one of the gpio pins for use as the system clock. in this fashion, only one crysta l oscillator is required for the entire system and the bom cost is reduced. the available clo ck frequencies and gpio configuration are discussed further in "8.2. microcontroller clock" on page 41. the si4330 may also be driven with an external 30 mhz cl ock signal through the xout pin. when driving with an external reference or using a tcxo, the xtal lo ad capacitance register should be set to 0. 5.8. regulators there are a total of six regulators integrated onto the si4330.with the exception of the digital regulator, all regulators are designed to operate with only internal de coupling. the digital regulator requires an external 1 f decoupling capacitor. all regulators are designed to operate with an input supply voltage from +1.8 to +3.6 v. a supply voltage should only be connected to the vdd pins. no voltage should be forced on the digital regulator outputs. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 09 r/w crystal oscillator load capacitance xtalshift xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 7fh
si4330-b1 32 rev 1.0 6. data handling and packet handler the internal modem is designed to operate with a packet including a 10101... preamble structure. to configure the modem to operate with packet formats without a preamble or other legacy packet st ructures contact customer support. 6.1. rx fifo a 64 byte fifo is integrated into the chip for rx, as shown in figure 11. "register 7fh. fifo access" is used to access the fifo. a burst read, as described in "3.1. serial peripheral interface (spi)" on page 16, from address 7fh will read data from the rx fifo. figure 10. fifo threshold the rx fifo has one programmable threshold called the fifo almost full threshold, rxafthr[5:0]. when the incoming rx data crosses the almost full threshold an interrupt will be gene rated to the microcontroller via the nirq pin. the microcontrolle r will then need to read t he data from the rx fifo. the rx fifo may be cleared or reset with the ffclrrx bit in ?register 08h. operating mode and function control 2,? on page 71. all interrupts may be enabled by setting the interrupt enabled bits in "register 05h. interrupt enable 1" and ?register 06h. interrupt enable 2,? on page 69. if the interrupt s are not enabled the fu nction will not generate an interrupt on the nirq pin but the bits will still be read correctly in the interrupt status registers. add r/w function/d escription d7 d6 d5 d4 d3 d2 d1 d0 por def. 08 r/w operating & function control 2 antdiv[2] antdiv[1] antdiv[0] rxmpk reserved enldm ffclrrx reserved 00h add r/w function/de scription d7 d6 d5 d4 d3 d2 d1 d0 por def. 7e r/w rx fifo control reserved reserved rxafthr[5] rxafthr[4] rxaf thr[3] rxafthr[2] rxafthr[1] rxafthr[0] 37h rx fifo rx fifo almost full threshold
si4330-b1 rev 1.0 33 6.2. packet configuration when using the fifo, automatic packet handling may be enabled for the rx mode. "register 30h. data access control" through ?register 39h. synchronization word 0,? on page 99 and ?register 3fh. check header 3,? on page 100 through ?register 4bh. received packet length ,? on page 104 control the configuration, status, and decoded rx packet data for packet handling. the general packet structure is shown in figure 12. the leng th of each field is shown below the field. the preamble pattern is always a series of alternating ones and zero es, starting with a zero. all the fields have programmable lengths to accommodate different applications. the most common crc polynominals are available for selection. figure 11. packet structure an overview of the packet handler conf iguration registers is shown in table 13. 6.3. packet handler rx mode 6.3.1. packet handler disabled when the packet handler is disabled certain fields in the received packet are still required. proper modem operation requires pream ble and sync when the fifo is being used, as shown in fi gure 14. bits after sync will be treated as raw data with no qualification. this mode allo ws for the creation of a custom packet handler when the automatic qualification parameters are not sufficient. manchester encoding is supported but data whitening, crc, and header checks are not figure 12. required rx packet structure with packet handler disabled 6.3.2. packet handler enabled when the packet handler is enabled, all the fields of the packet structure need to be configured. the receive fifo can be configured to handle packets of fixed or variable length with or without a header. if multiple packets are desired to be stored in the fifo, then there are options av ailable for the different fields that will be stored into the fifo. figure 15 demonstrates the options and settings available when multiple packets are enabled. figure 16 demonstrates the operation of fixed packet length and correct/incorrect packets. data preamble sync word header packet length crc 1- 512 bytes 1- 4 bytes 0-4 bytes 0 or 1 byte 0 or 2 bytes preamble sync data
si4330-b1 34 rev 1.0 figure 13. multiple packets in rx packet handler figure 14. multiple packets in rx with crc or header error register data register data fifo data h eader (s) l ength rx_multi_pk_en = 1 h data rx_multi_pk_en = 0 txhdlen = 0 txhdlen > 0 fixpklen fixpklen 0 1 01 data data data data l l h rx fifo contents: transmission: data l h data l h data l h data l h write pointer write pointer rx fifo addr. 63 0 rx fifo addr. 63 0 data l h write pointer rx fifo addr. 63 0 data l h data l h write pointer rx fifo addr. 63 0 crc error data l h data l h write pointer rx fifo addr. 63 0 initial state pk 1 ok pk 2 ok pk 3 error pk 4 ok
si4330-b1 rev 1.0 35 table 12. packet handler registers add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 30 r/w data access control enpacrx lsbfrst crcdonly *reserved reserved encrc crc[1] crc[0] 1dh 31 r ezmac status reserved rxcrc1 pksrch pkrx pkvalid crcerror reserved reserved ? 32 r/w header control 1 bcen[3] enbcast[2] enbcast[1 ] enbcast[0] hdch[3] hdch[2] hdch[1] hdch[0] 0ch 33 r/w header control 2 skipsyn hdlen[2] hdlen[1] hdl en[0] fixpklen synclen[1] synclen[0] prealen[8] 22h 34 r/w preamble length prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0] 07h 35 r/w preamble detection control preath[4] preath[3] preath[2] preath[1] preath[0] reserved reserved reserved 20h 36 r/w sync word 3 sync[31] sync[30] sync[29] sync[28] sync[27] sync[26] sync[25] sync[24] 2dh 37 r/w sync word 2 sync[23] sync[22] sync[21] sync[20] sync[19] sync[18] sync[17] sync[16] d4h 38 r/w sync word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[10] sync[9] sync[8] 00h 39 r/w sync word 0 sync[7] sync[6] sync[5] s ync[4] sync[3] sync[2] sync[1] sync[0] 00h 3a?3e r/w reserved reserved 3f r/w check header 3 chhd[31] chhd[30] chhd[29] chhd[28] chhd[27] chhd[26] chhd[25] chhd[24] 00h 40 r/w check header 2 chhd[23] chhd[22] chhd[21] chhd[20] chhd[19] chhd[18] chhd[17] chhd[16] 00h 41 r/w check header 1 chhd[15] chhd[14] chhd[13] chhd[12] chhd[11] chhd[10] chhd[9] chhd[8] 00h 42 r/w check header 0 chhd[7] chhd[6] chhd[5] chhd[4] chhd[3] chhd[2] chhd[1] chhd[0] 00h 43 r/w header enable 3 hden[31] hden[30] hden[29] hden[28] hden[27] hden[26] hden[25] hden[24] ffh 44 r/w header enable 2 hden[23] hden[22] hden[21] hden[20] hden[19] hden[18] hden[17] hden[16] ffh 45 r/w header enable 1 hden[15] hden[14] hden[13] hden[12] hden[11] hden[10] hden[9] hden[8] ffh 46 r/w header enable 0 hden[7] hden[6] hden[5] hden[4] hden[3] hden[2] hden[1] hden[0] ffh 47 r received header 3 rxhd[31] rxhd[30] rxhd[ 29] rxhd[28] rxhd[27] rxhd[26] rxhd[25] rxhd[24] ? 48 r received header 2 rxhd[23] rxhd[22] rxhd[ 21] rxhd[20] rxhd[19] rxhd[18] rxhd[17] rxhd[16] ? 49 r received header 1 rxhd[15] rxhd[14] rxhd[ 13] rxhd[12] rxhd[11] rxhd[10] rxhd[9] rxhd[8] ? 4a r received header 0 rxhd[7] rxhd[6] rxhd[5 ] rxhd[4] rxhd[3] rxhd[2] rxhd[1] rxhd[0] ? 4b r received packet length rxplen[7 ] rxplen[6] rxplen[5] rxplen[4] rxplen[3] rxplen[2] rxplen[1] rxplen[0] ?
si4330-b1 36 rev 1.0 6.4. data whitening, manchester encoding, and crc data whitening can be used to avoid extended sequences of 0s or 1s in the transmitted data stream to achieve a more uniform spectrum. when enabled, the payload dat a bits are xored with a pseudorandom sequence output from the built-in pn9 generator. the gene rator is initialized at th e beginning of the payload. the receiver recovers the original data by repeating this operation. manchester encoding can be used to ensure a dc-free transmission and good synchronization properties. when manchester encoding is used, the effective datarate is unchanged but the actual datarate (preamble length, etc.) is doubled du e to the nature of the encoding. the effective datarate when using manchester encoding is limited to 128 kbps. the implementation of ma nchester encoding is shown in figure 16. data whitening and manchester encoding can be selected with "register 70h. modulation mode control 1". the crc is configured via "register 30h. data acce ss control." figure 15 demonstrates the portions of the packet which have manchester encoding, data whitening, and crc applied. crc can be applied to only the data portion of the packet or to the data, packet length and he ader fields. figure 16 provides an example of how the manchester encoding is done and also the use of the manchester invert (enmaniv) function. figure 15. operation of data whitening, manchester encoding, and crc figure 16. manchester coding example 6.5. preamble detector the si4330 has integrated automatic pr eamble detection. the preamble length is configurable from 1?256 bytes using the prealen[7:0] field in "register 33h. header cont rol 2" and "register 34h. pr eamble length," as described in ?6.2. packet configuration.? the preamble detection threshold, preath[4:0] as set in "register 35h. preamble detection control 1", is in units of 4 bits. the preamble detector searches for a preamble pattern with a length of preath[4:0]. if a false preamble detect occurs, th e receiver will continuing searching fo r the preamble when no sync word is detected. when a false preamble detect occurs, the receiver will continuing searching fo r the preamble when no sync word is detected. on ce preamble is detected (false or real) then the part will then start searching for sync. if no sync occurs then a timeout will occur and the device will initiate search for preambl e again. the timeout period is defined as the sync word length plus four bits and will start after a no n-preamble pattern is recognized after a valid preamble detection. the preamble detector output may be programmed onto one of the gpio or read in the interrupt status registers. preamble sync header/ address pk length data crc crc (over data only) crc whitening manchester data before mancheste r data after machester ( manppol = 1, enmaninv = 0) data after machester ( manppol = 1, enmaninv = 1) data before manchester data after machester ( manppol = 0, enmaninv = 0) data after machester ( manppol = 0, enmaninv = 1) 111 11111 0 0001 000 0000 0 preamble = 0xff first 4bits of the synch. word = 0x2 preamble = 0x00 first 4bits of the synch. word = 0x2 0001 0
si4330-b1 rev 1.0 37 6.6. preamble length the preamble detection threshold determines the number of valid preamble bits the radio must receive to qualify a valid preamble. the preamble threshold should be adjusted depending on the nature of the application. the required preamble length th reshold will depend on when receive mode is entered in relation to the start of the transmitted packet and the length of the transmit prea mble. with a shorter than recommended preamble detection threshold the prob ability of false detection is directly related to how long the receiver oper ates on noise before the transmit preamble is received. false detection on noise may cause the actual packet to be missed. the preamble detection threshold is programmed in register 35h. for most applications with a pream ble length longer than 32 bits the default value of 20 is recommended for the preamble detection threshold. a shorter preamble detection threshold may be chosen if occasional false detections may be tolerated. when antenna diversity is enabled a 20- bit preamble detection threshold is recommended. when th e receiver is synchronously enabled just before the start of the packet, a shorter preamble detection thre shold may be used. table 13 demonstrates the recommended preamble detection threshold and preamble length for various modes. it is possible to use the si4330 in a raw mode without the requirement for a 101010 preamble. contact customer support for further details. note: the recommended preamble length and preamble detection threshold listed above are to achieve 0% per. they may be shortened when occasional packet errors are tolerable. 6.7. invalid preamble detector when scanning channels in a frequency hopping system it is desirable to deter mine if a channel is valid in the minimum amount of time. the preamble detector can outpu t an invalid preamble detect signal which can be used to identify the channel as invalid. after a configurable ti me set in register 60h[7:4], an invalid preamble detect signal is asserted indicating an invalid channel. the perio d for evaluating the signal for invalid preamble is defined as (inv_pre_th[3:0] x 4) x bit rate peri od. the preamble detect and invalid preamble detect signals are available in "register 03h. interrupt/status 1" and ?register 04h. interrupt/status 2? on page 66. 6.8. synchronization word configuration the synchronization word length for rx can be configured in reg 33h, synclen[1:0]. the expected or transmitted sync word can be configured from 1 to 4 bytes as defined below: ? synclen[1:0] = 00?expected synchronization word (sync word) 3. ? synclen[1:0] = 01?expected synchronization word 3 first, followed by sync word 2. ? synclen[1:0] = 10?expected synchronization word 3 first, followed by sync word 2, followed by sync word 1. ? synclen[1:0] = 1?expected synchronizat ion word 3 first, followed by sync word 2, followed by sync word 1, followed by sync word 0. the sync is transmitted or expected in the following sequence: sync 3 o sync 2 o sync 1 o sync 0. the sync word values can be programmed in registers 36h?39h. after preamb le detection, the part will search for sync for a fixed period of time. if a sync is not recognized in this period , a timeout will occur, and the search for preamble will be re- table 13. minimum receiver settling time mode approximate receiver settling time recommended preamble length with 8-bit detection threshold recommended preamble length with 20-bit detection threshold (g)fsk afc disabled 1 byte 20 bits 32 bits (g)fsk afc enabled 2 byte 28 bits 40 bits (g)fsk afc disabled +antenna diver- sity enabled 1 byte ? 64 bits (g)fsk afc enabled +antenna diversity enabled 2 byte ? 8 byte ook 2 byte 3 byte 4 byte ook + antenna diversity enabled 8 byte ? 8 byte
si4330-b1 38 rev 1.0 initiated. the timeout period after preamble detections is defined as the value programmed into the sync word length plus four additional bits. 6.9. receive header check the header check is designed to support 1?4 bytes and broadcast headers. the header length needs to be set in register 33h, hdlen[2:0]. the headers to be checked need to be set in register 32h, hdch[3:0]. for instance, there can be four bytes of header in the packet structure but on ly one byte of the header is set to be checked (i.e., header 3). for the headers that are set to be checked, the expected value of the header should be programmed in chhd[31:0] in registers 3f?42. the individual bits within the selected bytes to be checked can be enabled or disabled with the header enables, hden[31:0] in registers 43?46. for example, if you want to check all bits in header 3 then hden[31:24] should be set to ff but if only th e last 4 bits are desired to be checked then it should be set to 00001111 (0f). broadcast headers can also be programmed by setting bcen[3:0] in register 32h. for broadcast header check the value may be either ?ffh? or the value stored in the check header register. a logic equivalent of the header check for header 3 is shown in figure 17. a similar logic check will be done for header 2, header 1, and header 0 if enabled. figure 17. header bit wise rxhd[31:24] bit wise chhd[31:24] hden[31:24] = ffh hdch[3] header3_ok example for header 3 equivalence comparison = rxhd[31:24] equivalence comparison bcen[3]
si4330-b1 rev 1.0 39 7. rx modem configuration a microsoft excel (wds) parameter calculator or wirele ss development suite (wds) calculator is provided to determine the proper settings for the modem. the calculator can be found on www.silabs.com or on the cd provided with the demo kits. an application note is availabl e to describe how to use the calculator and to provide advanced descriptions of the m odem settings and calculations. 7.1. modem setti ngs for fsk and gfsk the modem performs channel selection and demodulation in the digital domain. the channel filter bandwidth is configurable from 2.6 to 620 khz. the receiver channel bandwidth is set depending on the data rate and modulation index via registers 1c?25h. the modulation index is equal to 2 times the peak deviation divided by the data rate (rb). when manchester coding is disabled, the required channel filter bandwidth is calculated as bw = 2fd + rb where fd is the frequency deviation and rb is the data rate.
si4330-b1 40 rev 1.0 8. auxiliary functions 8.1. smart reset the si4330 contains an enh anced integrated smart reset or por circuit. the por circuit contains both a classic level threshold reset as well as a slope detector po r. this reset circuit was designed to produce a reliable reset signal under any circumstan ces. reset will be initiated if an y of the following conditions occur: ? initial power on, vdd starts from gnd: reset is active till vdd reaches v rr (see table); ? when vdd decreases below v ld for any reason: reset is active till vdd reaches v rr ; ? a software reset via ?register 08h. operating mode and f unction control 2,? on page 71: reset is active for time t swrst ? on the rising edge of a vdd glitch when the supply voltage exceeds the followin g time functioned limit: figure 18. por glitch parameters the reset will initialize all regist ers to their default values. the reset signal is also av ailable for output and use by the microcontroller by using the default setting for gpio_0 . the inverted reset signal is available by default on gpio_1. table 14. por parameters parameter symbol comment min typ max unit release reset voltage vrr 0.85 1.3 1.75 v power-on vdd slope svdd tested vdd slope region 0.03 300 v/ms low vdd limit vld vld=0.4+t*0.2v/ms actual vdd(t) showing glitch reset limit: 0.4v+t*0.2v/ms vdd nom. 0.4v
si4330-b1 rev 1.0 41 8.2. microcontroller clock the 30 mhz crystal oscillator frequency is divided down in ternally and may be output to the microcontroller through gpio2. this feature is useful to lower bom cost by using only one crystal in the system. the system clock frequency is selectable from one of 8 options, as shown below. except for the 32.768 khz option, all other frequencies are derived by dividing the crystal oscillator frequency. the 32.7 68 khz clock signal is derived from an internal rc oscillator or an external 32 khz crystal. the default setting for gpio2 is to output the microcontroller clock signal with a frequency of 1 mhz. if the microcontroller clock option is being used there ma y be the need of a system clock for the microcontroller while the si4330 is in sleep mode. since the crystal oscillator is disabl ed in sleep mode in or der to save current, the low-power 32.768 khz clock can be automatically switched to become the microcontroller clock. this feature is called enable low frequency clock and is enabled by the en lfc bit in ?register 0ah. mi crocontroller output clock." when enlfc = 1 and the chip is in sleep mode then the 32.768 khz clock will be provided to the microcontroller as the system clock, regardless of the setting of mclk[2:0]. for example, if mclk[2:0] = 000, 30 mhz will be provided through the gpio output pin to the microcontroller as the system clock in all idle or rx states. when the chip enters sleep mode, the system clock will automatically switch to 32.768 kh z from the rc oscillator or 32.768 xtal. another available feature for the microcontroller clock is the clock tail, clkt[1:0] in ?register 0ah. microcontroller output clock." if the low frequency clock feature is not enabled (enlfc = 0), then the system clock to the microcontroller is disabled in sleep mode. however, it may be usef ul to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdo wn of the system clock signal. setting the clkt[1:0] field will provide additional cycl es of the system cloc k before it shuts off. if an interrupt is triggered, the microcontroller clock will remain enabled rega rdless of the selected mode. as soon as the interrupt is read the state ma chine will then move to the selected mode. the minimum current consumption will not be achieved until the interrup t is read. for instance, if the ch ip is commanded to sleep mode but an interrupt has occurred the 30 mhz xtal will not be disabled un til the interrupt has been cleared. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 0a r/w microcontroller output clock clkt [1] clkt[0] enlfc mclk[2] mclk[1] mclk[0] 06h mclk[2:0] clock frequency 000 30 mhz 001 15 mhz 010 10 mhz 011 4 mhz 100 3 mhz 101 2 mhz 110 1 mhz 111 32.768 khz clkt[1:0] clock tail 00 0 cycles 01 128 cycles 10 256 cycles 11 512 cycles
si4330-b1 42 rev 1.0 8.3. general purpose adc an 8-bit sar adc is integrated for general purpose use, as well as for digitizing the on-chip temperature sensor reading. registers 0fh "adc confi guration", 10h "sensor offset" and 4fh "amplifier offset" can be used to configure the adc operation. every time an adc conversion is desir ed, bit 7 "adcstart/adcbusy" in ?reg ister 1fh. clock recovery gearshift override? must be set to 1. this is a self clearing bit that will be reset to 0 at the end of the conversion cycle of the adc. the conversion time for the adc is 350 s. after this time or when the "a dcstart/adcbusy" bit is cleared, then the adc value may be read out of register 11h "adc value". the architecture of the adc is shown in figure 19. the signal and reference inputs of the adc are selected by adcsel[2:0] and adcref[1:0] in ?register 0fh. adc configurat ion,? respectively. the default setting is to read out the temperature sensor using the bandgap voltage (vbg) as re ference. with the vbg reference the input range of the adc is from 0?1.02 v with an lsb resolution of 4 mv (1 .02/255). changing the adc reference will change the lsb resolution accordingly. a differential multiplexer and amplifier are provided for inte rfacing external bridge sensors. the gain of the amplifier is selectable by adcgain[1:0] in regi ster 0fh. the majority of sensor bridges have supply voltage (vdd) dependent gain and offset. the reference voltage of the adc can be changed to either v dd /2 or v dd /3. a programmable v dd dependent offset voltage can be add ed using soffs[3:0] in register 10h. see ?an448: general purpose adc configuration? for mo re details on the usage of the general purpose adc. figure 19. general purpose adc architecture add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 0f r/w adc configuration adcstart/adcbusy adcsel[2] adcsel[1] adcsel[0] adcref[1] adcref[0] adcgain[1] adcgain[0] 00h 10 r/w sensor offset soffs[3] soffs[2] soffs[1] soffs[0] 00h 11 r adc value adc[7] adc[6] adc[5] adc[4] adc[3] adc[2] adc[1] adc[0] ? ? ? ? ? ? ? diff. mux diff. amp. input mux ref mux v in v ref ? ? adcsel [2:0] aoffs [4:0] adcgain [1:0] adcsel [2:0] adcref [1:0] adc [7:0] v dd / 3 v dd / 2 gpio1 gpio0 gpio2 temperature sensor v bg (1.2v) 8-bit adc 0 -1020mv / 0-255 soffs [3:0]
si4330-b1 rev 1.0 43 8.4. temperature sensor an integrated on-chip analog temperature sensor is av ailable. the temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the adc or when the analog temp voltage is selected on the analog test bus. the temperature sens or value may be digitized using the general-purpose adc and read out over the spi through "register 10h. adc s ensor amplifier offset." t he range of the temperature sensor is configurable. table 15 lists the settings for the different temperature ranges and performance. to use the temp sensor: 1. set the input for adc to the temperature sensor, "register 0fh. adc config uration"?adcsel[2:0] = 000 2. set the reference for adc, "register 0fh. adc configuration"?adcref[1:0] = 00 3. set the temperature range for adc, "register 12h. temperature sensor calibration"?tsrange[1:0] 4. set entsoffs = 1, "register 12h. temperature sensor calibration" 5. trigger adc reading, "register 0fh. adc configuration"?adcstart = 1 6. read temperature value?read contents of "register 11h. adc value" the slope of the temperature sensor is very linear and monotonic. for absolute accuracy better than 10 c calibration is necessary. the temperature sensor may be calibrated by setting entsoffs = 1 in ?register 12h. temperature sensor control? and settin g the offset with the tvoffs[7:0] bits in ?register 13h. temperature value offset.? this method adds a positive offset digitally to th e adc value that is read in ?r egister 11h. adc value.? the other method of calibration is to us e the tstrim which compensates the anal og circuit. this is done by setting entstrim = 1 and using the tstrim[2:0] bits to offset the temperature in ?register 12h. temperature sensor control.? with this method of calibration, a negative offset may be achieved. with both methods of calibration better than 3 c absolute accuracy may be achieved. the different ranges for the temperature sensor and adc8 are demonstrated in figure 20. the value of the adc8 may be translated to a temperature reading by adc8 value x adc8 lsb + lowest temperature in temp range. for instance for a tsrange = 00, temp = adc8value x 0.5 ? 64. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 12 r/w temperature sensor control tsrange[1] tsrange[0] entsoffs entstrim tstrim[3] tstrim[2] vbgtrim[1] vbgtrim[0] 20h 13 r/w temperature value offset tvoffs[7] tvoffs[6] tvoffs[5] tvoffs[4] tvoffs[3] tvoffs[2] tvoffs[1] tvoffs[0] 00h table 15. temperature sensor range entoff tsrange[1] tsrange[0] temp. range unit slope adc8 lsb 1 0 0 ?64 ? 64 c 8 mv/c 0.5 c 1 0 1 ?64 ? 192 c 4 mv/c 1 c 1 1 0 0 ? 128 c 8 mv/c 0.5 c 1 1 1 ?40 ? 216 f 4 mv/f 1 f 0* 1 0 0 ? 341 k 3 mv/k 1.333 k *note: absolute temperature mode, no temperature shift. this mode is only for test purposes. por value of en_toff is 1.
si4330-b1 44 rev 1.0 figure 20. temperature ranges using adc8 temperature measurement with adc8 0 50 100 150 200 250 300 - 40 - 20 0 20 40 60 80 100 temperature [celsius] sensor range 0 sensor range 1 sensor range 2 sensor range 3 adc v alue
si4330-b1 rev 1.0 45 8.5. low battery detector a low battery detector (lbd) with digital read-out is integr ated into the chip. a digital threshold may be programmed into the lbdt[4:0] field in "registe r 1ah. low battery detector threshol d." when the digitized battery voltage reaches this threshold an interrupt will be generated on the nirq pi n to the microcontroller. the microcontroller can confirm source of the interrupt by reading "register 03h. interrupt/status 1" and ?register 04h. interrupt/status 2,? on page 66. if the lbd is enabled while the chip is in sleep mode, it will automatically enable th e rc oscillator which will periodically turn on the lbd circuit to measure the battery voltage. the battery voltage may also be read out through "register 1bh. battery voltage level" at any time when the lbd is enabled. the low battery detect function is enabled by setting enlbd=1 in "register 0 7h. operating mode and function control 1". the lbd output is digitized by a 5-bit adc. when th e lbd function is enabled, enlbd = 1 in "register 07h. operating mode and function control 1", the battery volt age may be read at anytime by reading "register 1bh. battery voltage level." a battery voltage threshold may be programmed in ?register 1ah. low battery detector threshold." when the ba ttery voltage level drops below the battery vo ltage threshold an inte rrupt will be generated on the nirq pin to the microcontroller if the lbd interrupt is enabled in ?register 06h. interrupt enable 2,? on page 69. the microcontroller will then need to verify the interrupt by reading the interrupt status register, addresses 03 and 04h. the lsb step size for the lbd adc is 50 mv, with the adc range demonstrated in the table below. if the lbd is enabled the lbd and adc will automatically be enab led every 1 s for approximate ly 250 s to measure the voltage which minimizes the current consumption in sensor mode. before an interrupt is activated four consecutive readings are required. ad r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 1a r/w low battery detector threshold lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h 1b r battery voltage level 0 0 0 vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] ? adc value vdd voltage [v] 0< 1 . 7 1 1.7?1.75 2 1.75?1.8 ?? 29 3.1?3.15 30 3.15?3.2 31 > 3.2 adcvalue mv tage batteryvol ? ? ? 507.1
si4330-b1 46 rev 1.0 8.6. wake-up timer and 32 khz clock source the chip contains an in tegrated wake-up ti mer which can be used to periodica lly wake the chip from sleep mode. the wake-up timer runs from the internal 32.768 khz rc oscillator. the wake-up timer can be configured to run when in sleep mode. if enwt = 1 in "register 07h. operating mode and fu nction control 1" when entering sleep mode, the wake-up timer will c ount for a time specified def ined in registers 14?16h, "wake up timer period". at the expiration of this period an interr upt will be generated on the nirq pin if this interrupt is enabled. the microcontroller will then need to verify the interrupt by reading the register s 03h?04h, "interrupt status 1 & 2". the wake-up timer value may be read at any time by the wtv[15:0] read only registers 13h?14h. the formula for calculating the wake-up period is the following: use of the d variable in the formula is only necessary if fi ner resolution is required than can be achieved by using the r value. there are two differ ent methods for utilizing the wake -up timer (wut) depending on if the wut interrupt is enabled in ?register 06h. interrupt enable 2,? on page 69. if t he wut interrupt is enabled th en nirq pin will go low when the timer expires. the chip will also change state so that the 30 mhz xtal is enabled so that the microcontroller clock output is available for the microc ontroller to use to process the interrupt. the other method of use is to not enable the wut interrupt and use the wut gpio setting. in this mode of operation the chip will not change state until commanded by the microcontroller. the different modes of operating the wut and the current consumption impacts are demonstrated in figure 21. a 32 khz xtal may also be used for better timing accuracy . by setting the x32 ksel bit in ?register 07h. operating & function control 1," gpio0 is automatically reconfigured so that an external 32 khz xtal may be connected to this pin. in this mode, the gpio0 is extremely sensitiv e to parasitic capacitance, so only the xtal should be connected to this pin with the xtal physically located as close to the pin as possible. once the x32 ksel bit is set, all internal functions such as wut, micro-controller clock, and ldc mode will use the 32 khz xtal and not the 32 khz rc oscillator. wut register description wtr[3:0] r value in formula wtd[1:0] d value in formula wtm[15:0] m value in formula add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 14 r/w wake-up timer period 1 wtr[3 ] wtr[2] wtr[1] wtr[0] wtd[1] wtd[0] 00h 15 r/w wake-up timer period 2 wtm[15] wtm[14] w tm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h 16 r/w wake-up timer period 3 wtm[7] wtm[6 ] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 00h 17 r wake-up timer value 1 wtv[15] wtv[14] w tv[13] wtv[12] wtv[11] w tv[10] wtv[9] wtv[8] ? 18 r wake-up timer value 2 wtv[7] wtv[6] w tv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] ? ms m wut r 768.32 24 ?? ?
si4330-b1 rev 1.0 47 figure 21. wut interrupt and wut operation wut period gpiox = 00001 nirq spi interrupt read chip state current consumption sleep ready sleep ready sleep ready sleep 1 ua 1.5 ma 1.5 ma wut period gpiox = 00001 nirq spi interrupt read chip state current consumption sleep 1 ua interrupt enable enwut = 1 ( reg 06h) interrupt enable enwut = 0 ( reg 06h) 1 ua 1.5 ma 1 ua
si4330-b1 48 rev 1.0 8.7. low duty cycle mode the low duty cycle mode is available to automatically wake-up the receiver to check if a valid signal is available. the basic operation of the low duty cycle mode is demonstrated in the figure below. if a valid preamble or sync word is not detected the chip will return to sleep mode until the beg inning of a new wut period. if a valid preamble and sync are detected the receiver on period will be exte nded for the low duty cycl e mode duration (tldc) to receive all of the packet. the wut peri od must be set in conjunction with the low duty cycle mode duration. the r value (reg 14h) is shared between the wut and the tldc. th e ldc[7:0] bits are located in ?register 19h. low duty cycle mode duration.? the time of the tldc is determined by the formula below: figure 22. low duty cycle mode ms ldc tldc r 768.32 24 ]0:7[ ? ? ?
si4330-b1 rev 1.0 49 8.8. gpio configuration three general purpose ios (gpios) are available. nume rous functions such as s pecific interrupts, antenna diversity switch control, microcontrolle r output, etc. can be routed to the gpio pins as shown in the tables below. when in shutdown mode all the gpio pads are pulled low. note: the adc should not be selected as an input to the gpio in standby or sleep modes and will cause excess current con- sumption. the gpio settings for gpio1 and gpio2 are the same as for gpio0 with the except ion of the 00000 default setting. the default settings for each gpio are listed below: this application uses antenna diversity so a gpio is used to control the antenna switch. for a complete list of the available gpio's see ?an4670: si4330 register descriptions.? the gpio drive strength may be adjusted with the gpioxdrv[1:0] bits. setting a higher va lue will increase the drive strength and current capability of the gp io by changing the driver size. specia l care should be taken in setting the drive strength and loading on gpio2 wh en the microcontroller clock is used. excess loading or inadequate drive may contribute to increased spurious emissions. add r/w function/des cription d7 d6 d5 d4 d3 d2 d1 d0 por def. 0b r/w gpio0 configuration gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h 0c r/w gpio1 configuration gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h 0d r/w gpio2 configuration gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h 0e r/w i/o port configuration extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h gpio 00000?default setting gpio0 por gpio1 por inverted gpio2 microcontroller clock
si4330-b1 50 rev 1.0 8.9. antenna diversity to mitigate the problem of frequency-selective fading due to multi-path propagation, some radio systems use a scheme known as antenna diversity. in this schem e, two antennas are used. each time the radio enters rx mode the receive signal strength from each antenna is ev aluated. this evaluation process takes place during the preamble portion of the packet. the antenna with the stro ngest received signal is then used for the remainder of that rx packet. this chip fully supports antenna diversity with an integrated antenna dive rsity control algorithm. the required signals needed to control an external spdt rf switch (s uch as pin diode or gaas s witch) are available on the gpiox pins. the operation of these gpio signals is programmable to allow for different antenna diversity architectures and configurations. the antdiv[2:0] bits ar e found in register 08h ?operating & function control 2.? the gpio pins are capable of sourcing up to 5 ma of curr ent, so it may be used directly to forward-bias a pin diode if desired. the antenna diversity algorithm will automatically togg le back and forth between the antennas until the packet starts to arrive. the recommended preamble length for optimal antenna selection is 8 bytes. a special antenna diversity algorithm (antdiv[2:0] = 110 or 111) is included that allows for shorter preamble lengths for beacon mode in tdma-like systems where the arrival of the packet is synchronous to the receiver enable. the recommended preamble length to obtain optimal anten na selection for synchronous mode is 4 bytes. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 08 r/w operating & function control 2 antdiv[2] antdiv[1] antdiv[0] rxmpk reserved enldm ffclrrx reserved 00h table 16. antenna diversity control antdiv[2:0] rx state non rx state gpio ant1 gpio ant2 gpio ant1 gpio ant2 000 0 1 0 0 001 1 0 0 0 010 0 1 1 1 011 1 0 1 1 100 antenna diversity algorithm 0 0 101 antenna diversity algorithm 1 1 110 antenna diversity algorithm in beacon mode 0 0 111 antenna diversity algorithm in beacon mode 1 1
si4330-b1 rev 1.0 51 8.10. rssi and cl ear channel assessment received signal strength indicator (rssi) is an estimate of the signal strength in the channel to which the receiver is tuned. the rssi value can be read from an 8-bit regi ster with 0.5 db resolution per bit. figure 23 demonstrates the relationship between input power level and rssi value.the absolute va lue of the rssi will change slightly depending on the modem settings. the rssi may be read at anytime, but an incorrect error may rarely occur. the rssi value may be incorrect if read during the update period. the update period is approximately 10 ns every 4 tb. for 10 kbps, this would result in a 1 in 40,000 probability that th e rssi may be read incorrectly. this probability is extremely low, but to avoid this, one of the following optio ns is recommended: majority polling, reading the rssi value within 1 tb of the rssi interrupt, or using the rssi threshold described in the next paragraph for clear channel assessment (cca). for cca, threshold is programmed into rssith[7:0] in "reg ister 27h. rssi threshold fo r clear channel indicator." after the rssi is evaluated in the preamble, a decision is made if the signal strength on this channel is above or below the threshold. if the signal st rength is above the programmed threshold then the rssi status bit, irssi, in "register 04h. interrupt/st atus 2" will be set to 1. the rssi status can also be routed to a gpio line by configuring the gpio configuration register to gpiox[3:0] = 1110. figure 23. rssi value vs. input power add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 26 r received signal strength indicator rssi[7] rssi[6] rssi[5] rssi[4] rssi[3] rssi[2] rssi[1] rssi[0] ? 27 r/w rssi threshold for clear channel indicator rssith[7] rssith [6] rssith[5] rssith[4] rssith[3] rssith[2] rssith[1] rssith[0] 00h rssi vs input power 0 50 100 150 200 250 -120 -100 -80 -60 -40 -20 0 20 in pow [dbm] rssi
si4330-b1 52 rev 1.0 9. reference design reference designs are available at www.silabs.com for many common applications which include recommended schematics, bom, and layout. rx ma tching component values for differ ent frequency bands can be found in ?an427: ezradiopro si433x an d si443x rx lna matching.? %&'('
)* ++'*),- ',. ,-+ ,'./ 0* 1-,2 3&4 (') (') (') 5"/ ', 6 7)', & ( & ( & & % & % ! % & * & ( & * &8 3#9 : 3$ ;# ""< =& <> <= =& #= ?> < ?> < ?> < " =& ""<" ? " " &!@ =! = : 4 = "= > 4 < "" "" 7 8 a b 7 8 a b > freq. band lr cr1 cr2 [mhz] [nh] [pf] [pf] 434 33 4.7 10 470 27 4.7 12 868 11 3.9 6.8 915 11 3.3 6.8 si4330 revb1 rx matching figure 24. si4330 reference design schematic
si4330-b1 rev 1.0 53 10. application notes and reference designs a comprehensive set of application notes and reference de signs are available to assist with the development of a radio system. a partial list of applications notes is given below. for the complete list of applic ation notes, latest referenc e designs and demos visit the silicon labs website. ? an361: wireless mbus implementation using ezradiopro devices ? an379: antenna diversity with ezradiopro ? an414: ezradiopro layout design guide ? an415: ezradiopro programming guide ? an417: si4x3x family crystal oscillators ? an419: arib std-t67 narrow-band 426/429 mhz measured on the si4431-a0 ? an427: ezradiopro si433x and si443x rx lna matching ? an429: using the dc-dc converter on the f9xx seri es mcu for single battery operation with the ezradiopro rf devices ? an432: rx ber measurement on ez radiopro with a looped pn sequence ? an435: si4032/4432 pa matching ? an436: si4031/4431 pa matching ? an437: 915 mhz measurement results and fcc compliance ? an439: ezradiopro quick start guide ? an440: si4430/31/32 register descriptions ? an445: si4431 rf performance and etsi compliance test results ? an448: general purpose adc configuration ? an453: using the ezradiopro calculator and advanced rx bw calculations and settings ? an459: 950 mhz measurement results and arib compliance ? an460: 470 mhz measurement results for china ? an461:+24 dbm external pa application note and reference design ? an462: extended battery life using the ezradiopro and a dc-dc buck converter ? an463: support for non-standard packet structures and raw mode ? an466: si4030/31/32 register descriptions ? an467: si4330 register descriptions 11. customer support technical support fo r the complete family of silicon labs wireless products is ava ilable by accessing the wireless section of the silicon labs' website at www.silabs.com\wireless . for answers to common q uestions please visit the wireless knowledge base at www.silabs.com/support/knowledgebase .
si4330-b1 54 rev 1.0 12. register table and descriptions table 17. register descriptions add r/w function/desc data por default d7 d6 d5 d4 d3 d2 d1 d0 01 r device version 0 0 0 vc[4] vc[3] vc[2] vc[1] vc[0] 06h 02 r device status ffovfl ffunfl rxffem headerr reserved reserved cps[1] cps[0] ? 03 r interrupt status 1 ifferr reserved reser ved irxffafull iext reserved ipkvalid icrcerror ? 04 r interrupt status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor ? 05 r/w interrupt enable 1 enfferr reserved reserved enrxffafull enext reserved enpkvalid encrcerror 00h 06 r/w interrupt enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor 03h 07 r/w operating & function control 1 swres enlbd enwt x32ksel reserved rxon pllon xton 01h 08 r/w operating & function control 2 antdiv[2] antdiv[1] antdiv[0] rxmpk reserved enldm ffclrrx reserved 00h 09 r/w crystal oscillator load capacitance xtalshft xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 7fh 0a r/w microcontroller output clock reserved reser ved clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0] 06h 0b r/w gpio0 configuration gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h 0c r/w gpio1 configuration gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h 0d r/w gpio2 configuration gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h 0e r/w i/o port configuration reserved extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h 0f r/w adc configuration adcstart/ adc- done adcsel[2] adcsel[1] adcsel[0] adcref[1] adcref[0] adcgain[1] adcgain[0] 00h 10 r/w adc sensor amplifier offset reserved reserved reserv ed reserved adcoffs[3] adcoffs[2] adcoffs[1] adcoffs[0] 00h 11 r adc value adc[7] adc[6] adc[5] a dc[4] adc[3] adc[2] adc[1] adc[0] ? 12 r/w temperature sensor control tsrange[1] tsrange[0] entsoffs entstrim tstrim[3] tstrim[2] tstrim[1] tstrim[0] 20h 13 r/w temperature value offset tvoffs[7] tvoffs[6] tvoffs[5] tvoffs[4] tvoffs[3] tvoffs[2] tvoffs[1] tvoffs[0] 00h 14 r/w wake-up timer period 1 reserved reserved reserved wtr[4] wtr[3] wtr[2] wtr[1] wtr[0] 03h 15 r/w wake-up timer period 2 wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h 16 r/w wake-up timer period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 01h 17 r wake-up timer value 1 wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8] ? 18 r wake-up timer value 2 wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] ? 19 r/w low-duty cycle mode duration ldc[7] ldc[6] ldc[5] ldc[4] ldc[3] ldc[2] ldc[1] ldc[0] 00h 1a r/w low battery detector threshold reserved reserved reserved lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h 1b r battery voltage level 0 0 0 vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] ? 1c r/w if filter bandwidth dwn3_bypass ndec[2] ndec[1] ndec[0] filset[3] filset[2] filset[1] filset[0] 01h 1d r/w afc loop gearshift override afcbd enafc afcgearh[2] afcgearh[1] afcgearh[0] 1p5 bypass matap ph0size 40h 1e r/w afc timing control swait_timer[1] swait_timer[0] shwa it[2] shwait[1] shwait[0] anwait[2] anwait[1] anwait[0] 0ah 1f r/w clock recovery gearshift override reserved reserved crfast[2] c rfast[1] crfast[0] crslow[ 2] crslow[1] crslow[0] 03h 20 r/w clock recovery oversampling ratio rxosr[7] rxosr[6] rxosr[5] rxosr[4] rxosr[3] rxosr[ 2] rxosr[1] rxosr[0] 64h 21 r/w clock recovery offset 2 rxosr[10] rxosr[9] rxosr[8] stallctrl ncoff[19] ncoff[18] ncoff[17] ncoff[16] 01h 22 r/w clock recovery offset 1 ncoff[15] ncoff[14] ncoff[13] ncoff[12] ncoff[11] ncoff[10] ncoff[9] ncoff[8] 47h 23 r/w clock recovery offset 0 nco ff[7] ncoff[6] ncoff[5] ncoff[4] ncoff[3] ncoff[2] ncoff[1] ncoff[0] aeh 24 r/w clock recovery timing loop gain 1 reserved reserved reserved rxncocomp c rgain2x crgain[10] crgain[9] crgain[8] 02h 25 r/w clock recovery timing loop gain 0 crgain[7] crgain[6] crgain[5] crgain[4] crgain[3] crgain[2] crgain[1] crgain[0] 8fh 26 r received signal strength indi- cator rssi[7] rssi[6] rssi[5] rssi[4] rssi[3] rssi[2] rssi[1] rssi[0] ? 27 r/w rssi threshold for clear channel indicator rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] rssith[2] rssith[1] rssith[0] 1eh
si4330-b1 rev 1.0 55 28 r antenna diversity register 1 adrssi1[7] adrssia[6] adrs sia[5] adrssia[4] adrssia[3] adrssia[2] adrssia[1] adrssia[0] ? 29 r antenna diversity register 2 adrssib[7] adrssib[6] adrs sib[5] adrssib[4] adrssib[3] adrssib[2] adrssib[1] adrssib[0] ? 2a r/w afc limiter afclim[7] afclim[6] afclim[5] afclim[4] afclim[3] afclim[2] afclim[1] afclim[0] 00h 2b r afc correction read afc_corr[9] afc_corr[8] afc_corr[7] afc_corr[6] afc_corr[5] afc_corr[4] afc_corr[3] afc_corr[2] 00h 2c r/w ook counter value 1 afc_corr[9] afc_corr[9] ookfrzen peakdeten madeten ookcnt[10] ookcnt[9] ookcnt[8] 18h 2d r/w ook counter value 2 ookcnt[7] ookcnt[6] ookcnt[5] ookcnt[4] ookcnt[3] ookcnt[2] ookcnt[1] ookcnt[0] bch 2e r/w slicer peak hold reserved attack[2] attack[ 1] attack[0] decay[3] decay[2] decay[1] decay[0] 26h 2f reserved 30 r/w data access control enpacrx lsbfrst crc donly skip2ph reserved encrc crc[1] crc[0] 8dh 31 r ezmac status 0 rxcrc1 pksrch pkrx pk valid crcerror reserved reserved ? 32 r/w header control 1 bcen[3:0] hdch[3:0] 0ch 33 r/w header control 2 skipsyn hdlen[2] hdlen[1] hdlen[0] fixpklen synclen[1] synclen[0] prealen[8] 22h 34 r/w preamble length prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0] 08h 35 r/w preamble detection control preath[4] preath[3] preath[2] preath[1] preath[0] rssi_off[2] rssi_off[1] rssi_off[0] 2ah 36 r/w sync word 3 sync[31] sync[30] sync[29] sync[28] sync[27] sync[26] sync[25] sync[24] 2dh 37 r/w sync word 2 sync[23] sync[22] sync[21] sync[20] sync[19] sync[18] sync[17] sync[16] d4h 38 r/w sync word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[ 10] sync[9] sync[8] 00h 39 r/w sync word 0 sync[7] sync[6] sync[5] sync[4] sync[3] sync[2] sync[1] sync[0] 00h 3a-3e reserved 3f r/w check header 3 chhd[31] chhd[30] chhd[29] chhd[28] chhd[27] chhd[26] chhd[25] chhd[24] 00h 40 r/w check header 2 chhd[23] chhd[22] chhd[21] chhd[20] chhd[19] chhd[18] chhd[17] chhd[16] 00h 41 r/w check header 1 chhd[15] chhd[14] chhd[13] chhd[12] chhd[11] chhd[10] chhd[9] chhd[8] 00h 42 r/w check header 0 chhd[7] chhd[6] chhd[5] chhd[4] chhd[3] chhd[2] chhd[1] chhd[0] 00h 43 r/w header enable 3 hden[31] hden[30] hden[29] hden[28] hden[27] hden[26] hden[25] hden[24] ffh 44 r/w header enable 2 hden[23] hden[22] hden[21] hden[20] hden[19] hden[18] hden[17] hden[16] ffh 45 r/w header enable 1 hden[15] hden[14] hden[13] hden[12] hden[11] hden[10] hden[9] hden[8] ffh 46 r/w header enable 0 hden[7] hden[6] hden[5] hden[4] hden[3] hden[2] hden[1] hden[0] ffh 47 r received header 3 rxhd[31] rxhd[30] rxhd[29] rxhd[28] rxhd[27] rxhd[26] rxhd[25] rxhd[24] ? 48 r received header 2 rxhd[23] rxhd[22] rxhd[21] rxhd[20] rxhd[19] rxhd[18] rxhd[17] rxhd[16] ? 49 r received header 1 rxhd[15] rxhd[14] rxhd[13] rxhd[12] rxhd[11] rxhd[10] rxhd[9] rxhd[8] ? 4a r received header 0 rxhd[7] rxhd[6] rxhd[5] rxhd[4] rxhd[3] rxhd[2] rxhd[1] rxhd[0] ? 4b r received packet length rxplen[7] rxplen[6] rxplen [5] rxplen[4] rxplen[3] rxplen[2] rxplen[1] rxplen[0] ? 4c-4e reserved 4f r/w adc8 control reserved reserved adc8[5] adc8[4] adc8[3] adc8[2] adc8[1] adc8[0] 10h 50-5f reserved 60 r/w channel filter coefficient address inv_pre_th[3] inv_pre_th[2] inv_pre_th[1] inv_pre_th[0] chfiladd[3] chfiladd[2] chfiladd[1] chfiladd[0] 00h 61 reserved 62 r/w crystal oscillator/control test pwst[2] pwst[1] pwst[0] clkhyst enbias2x enamp2x bufovr enbuf 24h 63-68 reserved 69 r/w agc override 1 reserved sgi agcen lnagain pga3 pga2 pga1 pga0 20h 6a-6c reserved 70 r/w modulation mode control 1 reserved reserved enphpwdn manppol enmaninv enmanch enwhite 0ch 71 r/w modulation mode control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h 73 r/w frequency offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 74 r/w frequency offset 2 reserved reserved res erved reserved reserved reserved fo[9] fo[8] 00h table 17. register descriptions (continued) add r/w function/desc data por default d7 d6 d5 d4 d3 d2 d1 d0
si4330-b1 56 rev 1.0 note: detailed register descriptions are available in ?an467: si4330 register descriptions.? 75 r/w frequency band select reserved sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 75h 76 r/w nominal carrier frequency 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] bbh 77 r/w nominal carrier frequency 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h 78 reserved 79 r/w frequency hopping channel select fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h 7a r/w frequency hopping step size fhs[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1] fhs[0] 00h 7b reserved 7e r/w rx fifo control reserved reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0] 37h 7f r/w fifo access fifod[7] fifod[6] fifod[5] fifod[4] fifod[3] fifod[2] fifod[1] fifod[0] ? table 17. register descriptions (continued) add r/w function/desc data por default d7 d6 d5 d4 d3 d2 d1 d0
si4330-b1 rev 1.0 57 13. pin descriptions: si4330 pin pin name i/o description 1 vdd_rf vdd +1.8 to +3.6 v supply voltage input to all analog +1.7 v regulators. the recommended v dd supply voltage is +3.3 v. 2 nc ? no connect. 3r x p i differential rf input pins of the lna. see appl ication schematic for example matching network. 4r x n i 5 nc ? no connect. not connected internally to any circuitry. 6 ant1 o extra antenna or tr switch control to be used if more gpio are required. see register description of 08h. 7 gpio_0 i/o general purpose digital i/o that may be confi gured through the registers to perform various functions including: microcontroller clock ou tput, fifo status, por, wake-up timer, low battery detect, antenna switch, antdiversity control, etc. see the spi gpio configuration registers, address 0bh, 0ch, and 0dh for more information. 8 gpio_1 i/o 9 gpio_2 i/o 10 vr_dig o regulated output voltage of the digital 1.7 v regulator. a 1 f decoupling capacitor is required. 11 nc ? internally this pin is tied to the paddle of the package. this pin should be left unconnected or connected to gnd only. 12 vdd_dig vdd +1.8 to +3.6 v supply voltage input to the digital +1.7 v regulator. the recommended v dd supply voltage is +3.3 v. 13 sdo o 0?v dd v digital output that provides a serial readba ck function of the internal control registers. 14 sdi i serial data input. 0?v dd v digital input. this pin provides the seri al data stream for the 4-line serial data bus. 15 sclk i serial clock input. 0?v dd v digital input. this pin pr ovides the serial data cl ock function for the 4-line serial data bus. data is clocked into the si4330 on positive edge transitions. 16 nsel i serial interface select input. 0? v dd v digital input. this pin provides the select/enable function for the 4- line serial data bus. the signal is al so used to signify burst read/write mode. 17 nirq o general microcontroller interrupt status output. when the si4330 exhibits anyone of the interrupt events the nirq pin will be set low=0. please see the control logic registers section for more information on the interrupt events. the microcontroller can then deter mine the state of the interrupt by reading a corre- sponding spi interrupt status registers, address 03h and 04h. no external resistor pull-up is required, but it may be desirable if multiple interrupt lines are connected. 18 xout o crystal oscillator output. connect to an external 30 mhz crystal or to an external source. if using an external source with no crystal then dc coupling wi th a nominal 0.8 vdc level is recommended with a min- imum amplitude of 700 mvpp. 19 xin i crystal oscillator input. connect to an external 30 mhz crystal or leave fl oating when driving with an external source on xout. 20 sdn i shutdown input pin. 0?v dd v digital input. sdn should be = 0 in all modes except shutdown mode. when sdn =1 the chip will be completely shutdown and the contents of the registers will be lost. pkg paddle_gnd gnd the exposed metal paddle on the bottom of the si4330 supplies the rf and circuit ground(s) for the entire chip. it is very important that a good solder c onnection is made between this exposed metal paddle and the ground plane of the pcb underlying the si4330. gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 xout vr_dig sclk sdi sdo vdd_dig nc vdd_rf rxn gpio_2 gpio_1 nc nc rxp nirq sdn xin nsel gpio_0 ant1
si4330-b1 58 rev 1.0 14. ordering information part number* description package type operating temperature si4330-b1-fm ism ezradiopro receiver qfn-20 pb-free ?40 to 85 c *note: add an ?(r)? at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
si4330-b1 rev 1.0 59 15. package markings (top marks) 15.1. si4330 top mark 15.2. top mark explanation mark method: yag laser line 1 marking: x = part number 0 = si4330 line 2 marking: r = die revision b = revision b1 ttttt = internal code internal tracking code. line 3 marking: yy= year ww = workweek assigned by the assembly hous e. corresponds to the last significant digit of the year and workweek of the mold date.
si4330-b1 60 rev 1.0 16. package outline: si4330 figure 25 illustrates the package details for the si4330. table 23 lists the valu es for the dimensions shown in the illustration. figure 25. 20-pin quad flat no-lead (qfn) table 18. package dimensions symbol millimeters min nom max a 0 . 8 00 . 8 50 . 9 0 a1 0.00 0.02 0.05 b 0 . 1 80 . 2 50 . 3 0 d 4.00 bsc d2 2.55 2.60 2.65 e 0.50 bsc e 4.00 bsc e2 2.50 2.60 2.70 l 0 . 3 00 . 4 00 . 5 0 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 eee ? ? 0.10 notes: 1. all dimensions are shown in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si4330-b1 rev 1.0 61 17. pcb land pattern: si4330 figure 26 illustrates the pcb land pattern details for the si4330. table 24 lists the values for the dimensions shown in the illustration. figure 26. pcb land pattern
si4330-b1 62 rev 1.0 table 19. pcb land pattern dimensions symbol millimeters min max c1 3.90 4.00 c2 3.90 4.00 e 0.50 ref x1 0.20 0.30 x2 2.65 2.75 y1 0.65 0.75 y2 2.65 2.75 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. this land pattern design is based on ipc-7351 guidelines. note: solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes: stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness shou ld be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad. notes: card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si4330-b1 rev 1.0 63 d ocument c hange l ist revision 0.1 to revision 0.2 ? updated register descriptions revision 0.2 to revision 0.3 ? added max shutdown and standby currents and adjusted typical values. ? increased datarate to 256 kbps. ? updated table 10 on page 18. ? revised "7. rx modem configuration" on page 39. ? added sync and header sections for packet handler description ? updated descriptions on fifo and direct modes ? changed pin 5 to nc and pin 6 to ant1 ? updated "9. reference design" on page 52. ? moved detailed register descripti ons to application note (an440) ? moved measurement results to application note (an438) ? replaced applications sect ion with links to app notes
si4330-b1 64 rev 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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